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Sun, 04 Oct 2026 12:50:44 -0700 (PDT) Date: Sun, 4 Oct 2026 19:50:27 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20261004195027.227748-1-danielmentz@google.com> Subject: [PATCH v2] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses From: Daniel Mentz To: iommu@lists.linux.dev Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com, smostafa@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@linux.dev, jgg@ziepe.ca, praan@google.com, Daniel Mentz Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261004_125046_677929_1D55764D X-CRM114-Status: GOOD ( 14.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SMMU specification defines several types of SMMU-originated memory accesses, including Stage 1 and Stage 2 translation table walks, stream table accesses (L1STD and STE fetches), CD table accesses (L1CD and CD fetches), and queue accesses (CMDQ fetch, EVENTQ write, PRIQ write). While the memory attributes used for Stage 1 and Stage 2 translation table walks are configured in io-pgtable-arm based on whether the SMMU is coherent (ARM_SMMU_FEAT_COHERENCY), the attributes for stream tables, CD tables, and queues are currently hardcoded to Inner Shareable, Write-Back. On non-coherent systems, however, memory for stream tables, CD tables, and queues is allocated via dma_alloc_coherent() / dmam_alloc_coherent(), which provides CPU mappings with Normal Non-Cacheable attributes. Having a non-coherent SMMU access these buffers with Inner Shareable, Write-Back attributes results in mismatched memory attributes between the CPU and the SMMU. Configure the memory attributes for tables and queues in arm_smmu_device_reset() and arm_smmu_make_cdtable_ste() based on ARM_SMMU_FEAT_COHERENCY, matching the attributes used for translation table walks: - In SMMU_CR1, use Outer Shareable, Non-Cacheable for non-coherent SMMUs, while retaining Inner Shareable, Write-Back for coherent SMMUs. This applies to stream table accesses as well as queue accesses (CMDQ fetch, EVENTQ write, PRIQ write). - In STE.{S1CIR, S1COR, S1CSH}, use Outer Shareable, Non-Cacheable for non-coherent SMMUs, while retaining Inner Shareable, Write-Back Read-Allocate for coherent SMMUs. This applies to CD table accesses. Assisted-by: LLM Reviewed-by: Nicolin Chen Signed-off-by: Daniel Mentz --- Changes in v2: - Rename local variables 'cache' and 'sh' to 'cr1_cache' and 'cr1_sh' in arm_smmu_device_reset() (Nicolin, Will) - Collect Reviewed-by from Nicolin - Link to v1: https://lore.kernel.org/linux-iommu/20260929032229.3532247-1-danielmentz@google.com/ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 +++++++++++++++------ 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 34e916ea339f..02cc6fb83461 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1905,6 +1905,15 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, { struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; struct arm_smmu_device *smmu = master->smmu; + u64 s1c, s1csh; + + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) { + s1c = STRTAB_STE_1_S1C_CACHE_WBRA; + s1csh = ARM_SMMU_SH_ISH; + } else { + s1c = STRTAB_STE_1_S1C_CACHE_NC; + s1csh = ARM_SMMU_SH_OSH; + } memset(target, 0, sizeof(*target)); target->data[0] = cpu_to_le64( @@ -1916,9 +1925,9 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, target->data[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1DSS, s1dss) | - FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | - FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | - FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(STRTAB_STE_1_S1CIR, s1c) | + FIELD_PREP(STRTAB_STE_1_S1COR, s1c) | + FIELD_PREP(STRTAB_STE_1_S1CSH, s1csh) | ((smmu->features & ARM_SMMU_FEAT_STALLS && !master->stall_enabled) ? STRTAB_STE_1_S1STALLD : @@ -5102,7 +5111,7 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables, cr1_cache, cr1_sh; /* Clear CR0 and sync (disables SMMU and queue processing) */ reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); @@ -5116,12 +5125,20 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; /* CR1 (table and queue memory attributes) */ - reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | - FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | - FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | - FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | - FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | - FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) { + cr1_cache = CR1_CACHE_WB; + cr1_sh = ARM_SMMU_SH_ISH; + } else { + cr1_cache = CR1_CACHE_NC; + cr1_sh = ARM_SMMU_SH_OSH; + } + + reg = FIELD_PREP(CR1_TABLE_SH, cr1_sh) | + FIELD_PREP(CR1_TABLE_OC, cr1_cache) | + FIELD_PREP(CR1_TABLE_IC, cr1_cache) | + FIELD_PREP(CR1_QUEUE_SH, cr1_sh) | + FIELD_PREP(CR1_QUEUE_OC, cr1_cache) | + FIELD_PREP(CR1_QUEUE_IC, cr1_cache); writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); /* CR2 (random crap) */ -- 2.56.0.rc1.315.gc6ed9934b7-goog