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Introduce two macros: - MXC_ICR_REG(gpio): selects ICR1 (pins 0-15) or ICR2 (pins 16-31) - MXC_ICR_MASK(gpio): 2-bit mask at the correct position Use 0x3U in MXC_ICR_MASK() to avoid implementation-defined behavior when shifting by 30 bits (pin 15 or 31). Use field_prep() and field_get() from linux/bitfield.h for the shift/extract operations instead of open-coded shifts. The lowercase variants accept runtime-computed masks. This eliminates the intermediate 'bit' variable from both functions and makes the register access pattern self-documenting. No functional change. Signed-off-by: Peng Fan --- drivers/gpio/gpio-mxc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index d762d03c8d6a..c267727061fc 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -7,6 +7,7 @@ // Authors: Daniel Mack, Juergen Beisert. // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. +#include #include #include #include @@ -174,6 +175,9 @@ static inline bool mxc_gpio_has_power_off(struct mxc_gpio_port *port) #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) #define GPIO_INT_BOTH_EDGES 0x4 +#define MXC_ICR_REG(gpio) (GPIO_ICR1 + (((gpio) & 0x10) >> 2)) +#define MXC_ICR_MASK(gpio) (0x3U << (((gpio) & 0xf) << 1)) + static const struct of_device_id mxc_gpio_dt_ids[] = { { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, @@ -200,7 +204,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; - u32 bit, val; + u32 val; u32 gpio_idx = d->hwirq; int edge; void __iomem *reg = port->base; @@ -250,10 +254,9 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) } if (edge != GPIO_INT_BOTH_EDGES) { - reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ - bit = gpio_idx & 0xf; - val = readl(reg) & ~(0x3 << (bit << 1)); - writel(val | (edge << (bit << 1)), reg); + reg += MXC_ICR_REG(gpio_idx); + val = readl(reg) & ~MXC_ICR_MASK(gpio_idx); + writel(val | field_prep(MXC_ICR_MASK(gpio_idx), edge), reg); } writel(1 << gpio_idx, port->base + GPIO_ISR); @@ -266,16 +269,15 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg = port->base; - u32 bit, val; + u32 val; int edge; guard(gpio_generic_lock_irqsave)(&port->gen_gc); - reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ - bit = gpio & 0xf; + reg += MXC_ICR_REG(gpio); val = readl(reg); - edge = (val >> (bit << 1)) & 3; - val &= ~(0x3 << (bit << 1)); + edge = field_get(MXC_ICR_MASK(gpio), val); + val &= ~MXC_ICR_MASK(gpio); if (edge == GPIO_INT_HIGH_LEV) { edge = GPIO_INT_LOW_LEV; pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); @@ -287,7 +289,7 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) gpio, edge); return; } - writel(val | (edge << (bit << 1)), reg); + writel(val | field_prep(MXC_ICR_MASK(gpio), edge), reg); } /* handle 32 interrupts in one status register */ -- 2.51.0