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Mon, 5 Oct 2026 04:42:34 -0500 From: Dileep Kumar Nagavarapu To: Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Michal Simek , Conall O'Griofa CC: , , , , Dileep Kumar Nagavarapu , Sai Krishna Potthuri Subject: [PATCH v4 05/15] iio: adc: xilinx-xadc: Use bitfield helpers and bit macros Date: Mon, 5 Oct 2026 15:11:55 +0530 Message-ID: <20261005094205.1045874-6-dileepkumar.nagavarapu@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261005094205.1045874-1-dileepkumar.nagavarapu@amd.com> References: <20261005094205.1045874-1-dileepkumar.nagavarapu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B072:EE_|SN7PR12MB7203:EE_ X-MS-Office365-Filtering-Correlation-Id: 68002387-73a2-4ef1-1c83-08df22c4fec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|23010399003|82310400026|18002099003|22082099003|11063799006|56012099006|10067099003; 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Using the kernel bitfield helpers improves readability and makes bit operations less error-prone. No functional changes intended. Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Dileep Kumar Nagavarapu --- drivers/iio/adc/xilinx-xadc-core.c | 25 +++++++++++++------------ drivers/iio/adc/xilinx-xadc.h | 24 ++++++++++++------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index b4a3e6f967c4..9e4955016bbc 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -11,6 +11,8 @@ * - AXI XADC interface: Xilinx PG019 */ +#include +#include #include #include #include @@ -47,18 +49,17 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; #define XADC_ZYNQ_REG_CTL 0x18 #define XADC_ZYNQ_CFG_ENABLE BIT(31) -#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16) -#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16 #define XADC_ZYNQ_CFG_REDGE BIT(12) -#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8) -#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8) -#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8) -#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8) -#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8) +#define XADC_ZYNQ_CFG_DFIFOTH_MASK GENMASK(19, 16) +#define XADC_ZYNQ_CFG_TCKRATE_MASK GENMASK(9, 8) +#define XADC_ZYNQ_CFG_TCKRATE_DIV2 0 +#define XADC_ZYNQ_CFG_TCKRATE_DIV4 BIT(8) +#define XADC_ZYNQ_CFG_TCKRATE_DIV8 BIT(9) +#define XADC_ZYNQ_CFG_TCKRATE_DIV16 GENMASK(9, 8) #define XADC_ZYNQ_CFG_IGAP(x) (x) #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8) -#define XADC_ZYNQ_INT_ALARM_MASK 0xff +#define XADC_ZYNQ_INT_ALARM_MASK GENMASK(7, 0) #define XADC_ZYNQ_STATUS_DFIFOE BIT(8) @@ -86,7 +87,7 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500; #define XADC_AXI_GIER_ENABLE BIT(31) #define XADC_AXI_INT_EOS BIT(4) -#define XADC_AXI_INT_ALARM_MASK 0x3c0f +#define XADC_AXI_INT_ALARM_MASK (GENMASK(13, 10) | GENMASK(3, 0)) #define XADC_FLAGS_BUFFERED BIT(0) #define XADC_FLAGS_IRQ_OPTIONAL BIT(1) @@ -196,7 +197,7 @@ static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val) xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd)); xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp); tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK; - tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET; + tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1); xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp); xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0); @@ -857,7 +858,7 @@ static int xadc_read_samplerate(struct xadc *xadc) if (ret) return ret; - div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET; + div = FIELD_GET(XADC_CONF2_DIV_MASK, val16); if (div < 2) div = 2; @@ -965,7 +966,7 @@ static int xadc_write_samplerate(struct xadc *xadc, int val) div = 0xff; return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK, - div << XADC_CONF2_DIV_OFFSET); + FIELD_PREP(XADC_CONF2_DIV_MASK, div)); } static int xadc_write_raw(struct iio_dev *indio_dev, diff --git a/drivers/iio/adc/xilinx-xadc.h b/drivers/iio/adc/xilinx-xadc.h index 8449fb741370..a659b7981b2f 100644 --- a/drivers/iio/adc/xilinx-xadc.h +++ b/drivers/iio/adc/xilinx-xadc.h @@ -9,6 +9,7 @@ #ifndef __IIO_XILINX_XADC__ #define __IIO_XILINX_XADC__ +#include #include #include #include @@ -141,20 +142,19 @@ static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 va #define XADC_CONF0_MUX BIT(11) #define XADC_CONF0_CHAN(x) (x) -#define XADC_CONF1_SEQ_MASK (0xf << 12) -#define XADC_CONF1_SEQ_DEFAULT (0 << 12) -#define XADC_CONF1_SEQ_CONTINUOUS (2 << 12) -#define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12) -#define XADC_CONF1_SEQ_INDEPENDENT (8 << 12) -#define XADC_CONF1_ALARM_MASK 0x0f0f +#define XADC_CONF1_SEQ_MASK GENMASK(15, 12) +#define XADC_CONF1_SEQ_DEFAULT 0 +#define XADC_CONF1_SEQ_CONTINUOUS BIT(13) +#define XADC_CONF1_SEQ_SIMULTANEOUS BIT(14) +#define XADC_CONF1_SEQ_INDEPENDENT BIT(15) +#define XADC_CONF1_ALARM_MASK (GENMASK(11, 8) | GENMASK(3, 0)) -#define XADC_CONF2_DIV_MASK 0xff00 -#define XADC_CONF2_DIV_OFFSET 8 +#define XADC_CONF2_DIV_MASK GENMASK(15, 8) -#define XADC_CONF2_PD_MASK (0x3 << 4) -#define XADC_CONF2_PD_NONE (0x0 << 4) -#define XADC_CONF2_PD_ADC_B (0x2 << 4) -#define XADC_CONF2_PD_BOTH (0x3 << 4) +#define XADC_CONF2_PD_MASK GENMASK(5, 4) +#define XADC_CONF2_PD_NONE 0 +#define XADC_CONF2_PD_ADC_B BIT(5) +#define XADC_CONF2_PD_BOTH GENMASK(5, 4) #define XADC_ALARM_VCCINT_MASK BIT(1) #define XADC_ALARM_VCCAUX_MASK BIT(2) -- 2.34.1