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([179.179.237.181]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-35146ac4dc4sm140223eec.23.2026.10.05.11.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 11:31:07 -0700 (PDT) From: Vinicius Pedrosa To: Junhui Liu , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms Subject: Re: [PATCH v5 3/8] clk: sunxi-ng: a733: Add PRCM CCU Date: Mon, 5 Oct 2026 15:30:20 -0300 Message-ID: <20261005183038.417798-1-vinicius.eduardo.pedrosa@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260930-a733-clk-v5-3-11175b41cd2d@pigmoral.tech> References: <20260930-a733-clk-v5-0-11175b41cd2d@pigmoral.tech> <20260930-a733-clk-v5-3-11175b41cd2d@pigmoral.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_113113_573625_3E45A03F X-CRM114-Status: GOOD ( 10.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Junhui, On Wed Sep 30, 2026 at 1:26 AM CST, Junhui Liu wrote: > +static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0); [...] > +static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw, > + 0x21c, BIT(0), 0); I'm bringing up mainline on a Radxa Cubie A7Z (PCB V1.11, 1 GiB). With 7.3-rc6, this series and a local common-DT integration, PSCI reboot and power-off hang once unused clocks are disabled. The boot chain uses vendor boot0/BL31 and source-built SCP/U-Boot. Keeping both of these gates enabled fixes reboot; either alone still hangs. With only these two marked CLK_IS_CRITICAL, reboot returns to boot0 and power-off drops DCDC1 from 3.3 V to 0.7 V and turns off the green LED with power still connected. I haven't checked whether each gate is needed for power-off on its own. My guess is that BL31 talks to the SCP for these, but I haven't traced it, and it may be specific to the vendor firmware. Would it make sense to mark them CLK_IS_CRITICAL, like bus-r-cpucfg already is? I can test the next revision on this board either way. Thanks, Vinicius