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Mon, 05 Oct 2026 15:59:54 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-88b0b8f5b79sm4183327b3a.15.2026.10.05.15.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2026 15:59:52 -0700 (PDT) From: Coia Prant To: Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v11 0/2] phy: rockchip: naneng-combphy: add SGMII MAC selection for RK3568 Date: Tue, 6 Oct 2026 06:59:42 +0800 Message-ID: <20261005225944.1171574-1-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261005_155955_639290_68E36D86 X-CRM114-Status: GOOD ( 11.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Changes since v10: - Drop the top-level "default: 1" for "rockchip,sgmii-mac-sel". dtschema injects top-level defaults into every matching node, and the injected value conflicts with the "else" branch that forbids the property on non-RK3568 variants, breaking dtbs_check on those platforms. The driver already treats an absent property as 1 (GMAC1), so behavior is unchanged. === This is the PHY part split out from the v10 RK3568 SGMII series, sent separately to linux-phy as suggested by Vinod and Jakub. On RK3568, the SGMII interface can be routed to either GMAC0 or GMAC1 via the GRF register pipe_sgmii_mac_sel. Patch 1 documents the "rockchip,sgmii-mac-sel" DT property, patch 2 adds the driver support. >From the RK3568 TRM (Part1, Page 229), PIPE_GRF_XPCS_CON0 bit 1 (pipe_sgmii_mac_sel) is defined as: 0: SGMII routed to GMAC0 1: SGMII routed to GMAC1 The hardware reset value is 1 (GMAC1). If the property is set to 0, the driver routes SGMII to GMAC0; if set to 1 (or omitted), it remains at GMAC1. This is necessary for boards such as the Ariaboard Photonicat, which uses the SGMII interface connected to GMAC0. The DTS changes using this property are sent separately to Heiko/linux-rockchip, and the net-next parts (XPCS glue, dwmac-rk SGMII support) are sent separately to net-next. There is no hard build dependency; the pieces can converge during the merge window. --- Coia Prant (2): dt-bindings: phy: rockchip: naneng-combphy: add rockchip,sgmii-mac-sel property phy: rockchip: naneng-combphy: add SGMII MAC selection for RK3568 .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 12 ++++++++++++ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++ 2 files changed, 20 insertions(+) -- 2.47.3