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Wed, 7 Oct 2026 17:14:06 +0200 From: Antonio Borneo To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , , , , CC: Antonio Borneo , Amelie Delaunay Subject: [PATCH 1/3] ARM: dts: stm32: enable iwdg1 on STM32MP15 ST boards Date: Wed, 7 Oct 2026 17:13:56 +0200 Message-ID: <20261007151358.1166329-2-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261007151358.1166329-1-antonio.borneo@foss.st.com> References: <20261007151358.1166329-1-antonio.borneo@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.252.9.73] X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE2.st.com (10.75.128.133) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MI3PEPF0000848D:EE_|GV1PR10MB6100:EE_ X-MS-Office365-Filtering-Correlation-Id: d9aaaca6-b341-4253-4581-08df2485d683 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|23010399003|56012099006|11063799006|10067099003|22082099003|18002099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FmvwnuvYaGgyQ6Pgiecw+rL15xm3rTaOAynjwBuCH26LEIN22zIAOpBAlNGNM8oJQ37sp3gLDOH4EylAwHAHt44dtDMYJKU4YoDlecG3PUHVtBg/RsdZyJlDSXlGwh6BrIcFoow3ZQzY+H2Akma43suUgKHb5wCWKQsmqLZbhpcw/daYOdvaWjxvCjskI2j7/dIuVv1yf7P2P/kESw0NlypZhcYyoO5ZwmBjmxXDS5TT4xb74tM7gmrrU+AT+vYr+EdLMJZsKobBwkwAvA2ECmlWQn6GQfxFJx0GFHL0IOklEvVkUWLmvccqjGx1w6jEcYvJlXjpJeQVswU1TbngqchaWKVrciRh4/q6HcMqxeQha69A5kXcsOdCkkMO1y7NSs+o4ylbICICRarLyTD7IqtT1Cw5rVIeQ+9gHZ7ggoD7zgArRS2orb8E5l9cmj01 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2026 15:15:35.7258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9aaaca6-b341-4253-4581-08df2485d683 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: MI3PEPF0000848D.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR10MB6100 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261007_081545_233744_0B6D75F8 X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Amelie Delaunay On ST STM32MP15 boards where IWDG1 is exposed as a non-secure watchdog, Linux must register and periodically ping it once started by the boot chain. Add the missing IWDG1 DT node to the STM32MP151 SoC device tree and enable it on ST non-SCMI boards that use the non-secure watchdog configuration. Signed-off-by: Amelie Delaunay Signed-off-by: Antonio Borneo --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 4 ++++ arch/arm/boot/dts/st/stm32mp151.dtsi | 9 +++++++++ arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 5 +++++ 4 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi index 98552fe45d4e0..cc9521b105262 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -64,6 +64,10 @@ scmi_usb33: regulator@2 { }; }; +&iwdg1 { + status = "disabled"; +}; + ®11 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index e7fec8b49ae16..25f111c8aa7a4 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -570,6 +570,15 @@ usbphyc_port1: usb-phy@1 { }; }; + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = ; + clocks = <&rcc IWDG1>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index 49dd555cc228c..dfe726b481629 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -331,6 +331,11 @@ &ipcc { status = "okay"; }; +&iwdg1 { + timeout-sec = <32>; + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 1a07ae09afb2a..e8e75e59f4c98 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -511,6 +511,11 @@ &ipcc { status = "okay"; }; +&iwdg1 { + timeout-sec = <32>; + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; -- 2.34.1