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[2a02:3100:ad61:5a01:743c:891f:b33c:cae7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48c71d1f8fbsm8458219f8f.33.2026.10.07.22.37.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 07 Oct 2026 22:37:58 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] ARM: cmpxchg: support 2-byte xchg() on pre-ARMv6 CPUs Date: Thu, 8 Oct 2026 07:37:42 +0200 Message-Id: <20261008053746.49631-3-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261008053746.49631-1-kmehltretter@gmail.com> References: <20261008053746.49631-1-kmehltretter@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261007_223800_821822_E7B8F0CD X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Pre-ARMv6 CPUs have no halfword swp, so __arch_xchg() only handles 1- and 4-byte exchanges there and turns any other size into a link error via __bad_xchg(). No C code needs a 16-bit xchg() on these CPUs, but the Rust atomic helpers in rust/helpers/atomic_ext.c provide xchg() for Atomic unconditionally, so building with CONFIG_RUST=y for ARMv5 fails: ld.lld: error: undefined symbol: __bad_xchg >>> referenced by helpers.c >>> rust/helpers/helpers.o:(rust_helper_atomic_i16_xchg) Implement the 2-byte case with interrupts disabled, as the pre-ARMv6 atomic_t operations already do. This is safe because a kernel built for ARMv5 or older is never SMP. ARMv6 before ARMv6K (ARM1136r0) has no 16-bit exclusive access either. It is not handled here. Rust stays disabled for those kernels, and they cannot be SMP since commit d70242427110 ("ARM: rework ARM11 CPU selection logic"). Acked-by: Arnd Bergmann Reviewed-by: Linus Walleij Reviewed-by: Bradley Morgan Assisted-by: LLM Signed-off-by: Karl Mehltretter --- arch/arm/include/asm/cmpxchg.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 0ce5225af442..18555ae22893 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -31,11 +31,10 @@ __arch_xchg(unsigned long x, volatile void *ptr, int size) { extern void __bad_xchg(volatile void *, int); unsigned long ret; -#ifdef swp_is_buggy - unsigned long flags; -#endif #if __LINUX_ARM_ARCH__ >= 6 unsigned int tmp; +#else + unsigned long flags; #endif prefetchw((const void *)ptr); @@ -106,6 +105,15 @@ __arch_xchg(unsigned long x, volatile void *ptr, int size) : "r" (x), "r" (ptr) : "memory", "cc"); break; +#endif +#if __LINUX_ARM_ARCH__ < 6 + case 2: + /* swp has no halfword form. Pre-ARMv6 is never SMP. */ + raw_local_irq_save(flags); + ret = *(volatile unsigned short *)ptr; + *(volatile unsigned short *)ptr = x; + raw_local_irq_restore(flags); + break; #endif default: /* Cause a link-time error, the xchg() size is not supported */ -- 2.39.5 (Apple Git-154)