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[92.76.89.226]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b1c1d9fc0esm1477287a12.4.2026.10.12.07.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 07:04:51 -0700 (PDT) From: Thilo Zirnstein To: michal.simek@amd.com, andi.shyti@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Thilo Zirnstein Subject: [PATCH 1/1] i2c: i2c-xiic: fix clearing of bnb irq Date: Mon, 12 Oct 2026 16:04:44 +0200 Message-ID: <20261012140444.1195207-1-thi.zirnstein@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261012_070456_345515_76D0DF9E X-CRM114-Status: GOOD ( 29.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This commit fixes the clearing routine for the bus not busy (bnb) irq. The bnb is used to indicate that the current transfer is done. A high level view of the software flow for tx: * init i2c controller * prepare all registers ( fill fifo, enable irqs, ... ) * start i2c txfer * clear and enable bnb * wait for completion * ( serve interrupts ) * ( bnb interrupt ): complete completion The datasheet ( pg090-axi-iic, Interrupt-Status-Register ISR) states that the bnb bit can only be cleared if the bus busy bit in the status register is set. So the iic controller must have recognized that their is some activity on the bus. ( Start condition ) Currently the bnb bit is cleared without checking or waiting for this condition. This can lead to spurious bnb interrupts. This commit introduces a function for clearing the bnb bit, which waits for all preconditions and clears the bnb bit or times out. Tested on Zynqmp dev board with some custom logic. Tested-by: Thilo Zirnstein Signed-off-by: Thilo Zirnstein --- drivers/i2c/busses/i2c-xiic.c | 103 ++++++++++++++++------------------ 1 file changed, 48 insertions(+), 55 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 5e397a7e63f6..de463d356bff 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -73,9 +73,6 @@ enum i2c_scl_freq { * @prev_msg_tx: Previous message is Tx * @quirks: To hold platform specific bug info * @smbus_block_read: Flag to handle block read - * @smbus_actual_len: Valid byte count (length + payload + optional PEC) of a - * padded SMBus block read. msg->len is trimmed to this on completion. - * Zero when no trimming is needed. * @input_clk: Input clock to I2C controller * @i2c_clk: I2C SCL frequency * @atomic: Mode of transfer @@ -101,7 +98,6 @@ struct xiic_i2c { bool prev_msg_tx; u32 quirks; bool smbus_block_read; - unsigned int smbus_actual_len; unsigned long input_clk; unsigned int i2c_clk; bool atomic; @@ -230,7 +226,9 @@ static const struct timing_regs timing_reg_values[] = { #define XIIC_RESET_MASK 0xAUL -#define XIIC_PM_TIMEOUT 1000 /* ms */ +#define XIIC_PM_TIMEOUT 1000 /* ms */ +/* timeout waiting for bus busy */ +#define XIIC_BB_TIMEOUT (msecs_to_jiffies(1)) /* timeout waiting for the controller to respond */ #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) /* timeout waiting for the controller finish transfers */ @@ -392,6 +390,30 @@ static int xiic_wait_tx_empty(struct xiic_i2c *i2c) return 0; } +static int xiic_clear_en_bnb(struct xiic_i2c *i2c) +{ + u8 sr = 0, isr = 0; + unsigned long timeout; + + timeout = jiffies + XIIC_BB_TIMEOUT; + for (isr = xiic_getreg8(i2c, XIIC_IISR_OFFSET); + (isr & XIIC_INTR_BNB_MASK); + isr = xiic_getreg8(i2c, XIIC_IISR_OFFSET)) { + + sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); + if (sr & XIIC_SR_BUS_BUSY_MASK) + xiic_setreg8(i2c, XIIC_IISR_OFFSET, XIIC_INTR_BNB_MASK); + + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Failed to clear bnb\n"); + return -ETIMEDOUT; + } + } + + xiic_irq_en(i2c, XIIC_INTR_BNB_MASK); + return 0; +} + /** * xiic_setclk - Sets the configured clock rate * @i2c: Pointer to the xiic device structure @@ -543,38 +565,30 @@ static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) /* Check if received length is valid */ if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) { - unsigned int pec_len = i2c->rx_msg->len - 1; - /* Set Receive fifo depth */ - if (rxmsg_len + pec_len > IIC_RX_FIFO_DEPTH) { + if (rxmsg_len > IIC_RX_FIFO_DEPTH) { /* - * Trailing bytes (payload plus any PEC) exceed Rx FIFO - * capacity, so drain in chunks. This also keeps the - * else branch below from pushing rfd_set past the - * 4-bit XIIC_RFD_REG_OFFSET field. + * When Rx msg len greater than or equal to Rx fifo capacity + * Receive fifo depth should set to Rx fifo capacity minus 1 */ rfd_set = IIC_RX_FIFO_DEPTH - 1; - i2c->rx_msg->len = rxmsg_len + 1 + pec_len; - } else if (1 + rxmsg_len + pec_len < SMBUS_BLOCK_READ_MIN_LEN) { + i2c->rx_msg->len = rxmsg_len + 1; + } else if ((rxmsg_len == 1) || + (rxmsg_len == 0)) { /* - * The HW needs SMBUS_BLOCK_READ_MIN_LEN bytes on the - * bus to exit cleanly: by the time the ISR reads the - * length byte the second byte is already being clocked - * in, too late to NACK. Pad the drain target and record - * the real length, trimmed back on completion so the - * PEC check sees the right byte. + * Minimum of 3 bytes required to exit cleanly. 1 byte + * already received, Second byte is being received. Have + * to set NACK in read_rx before receiving the last byte */ rfd_set = 0; i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN; - i2c->smbus_actual_len = 1 + rxmsg_len + pec_len; } else { /* - * All trailing bytes fit in the Rx FIFO. Defer RX_FULL - * until every one of them is buffered, so the drain - * takes xiic_read_rx()'s bytes_rem == 0 path. + * When Rx msg len less than Rx fifo capacity + * Receive fifo depth should set to Rx msg len minus 2 */ - rfd_set = rxmsg_len + pec_len - 1; - i2c->rx_msg->len = rxmsg_len + 1 + pec_len; + rfd_set = rxmsg_len - 2; + i2c->rx_msg->len = rxmsg_len + 1; } xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set); @@ -587,16 +601,6 @@ static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c) dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n"); } -/* - * Undo the setup-time padding of a short SMBus block read before rx_msg is - * cleared, so the PEC check sees the right byte. - */ -static void xiic_smbus_trim_len(struct xiic_i2c *i2c) -{ - if (i2c->rx_msg && i2c->smbus_actual_len) - i2c->rx_msg->len = i2c->smbus_actual_len; -} - static void xiic_read_rx(struct xiic_i2c *i2c) { u8 bytes_in_fifo, cr = 0, bytes_to_read = 0; @@ -819,8 +823,6 @@ static irqreturn_t xiic_process(int irq, void *dev_id) xiic_read_rx(i2c); if (xiic_rx_space(i2c) == 0) { - xiic_smbus_trim_len(i2c); - /* this is the last part of the message */ i2c->rx_msg = NULL; @@ -881,19 +883,13 @@ static irqreturn_t xiic_process(int irq, void *dev_id) } if (pend & XIIC_INTR_BNB_MASK) { - /* IIC bus has transitioned to not busy */ - clr |= XIIC_INTR_BNB_MASK; - /* The bus is not busy, disable BusNotBusy interrupt */ xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); if (i2c->tx_msg && i2c->smbus_block_read) { i2c->smbus_block_read = false; - /* - * Drive xiic_tx_space() to 0 to signal STATE_DONE - * without truncating the rx_msg length. - */ - i2c->tx_pos = i2c->tx_msg->len; + /* Set requested message len=1 to indicate STATE_DONE */ + i2c->tx_msg->len = 1; } if (!i2c->tx_msg) @@ -965,7 +961,6 @@ static void xiic_recv_atomic(struct xiic_i2c *i2c) return; } - xiic_smbus_trim_len(i2c); i2c->rx_msg = NULL; xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK); @@ -983,9 +978,6 @@ static void xiic_start_recv(struct xiic_i2c *i2c) u8 cr = 0, rfd_set = 0; struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; - /* A stale value from an aborted block read would truncate this msg. */ - i2c->smbus_actual_len = 0; - if (!i2c->atomic) dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), @@ -1028,7 +1020,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + xiic_clear_en_bnb(i2c); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty @@ -1095,7 +1087,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c) if (i2c->nmsgs == 1) /* very last, enable bus not busy as well */ - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + xiic_clear_en_bnb(i2c); /* the message is tx:ed */ i2c->tx_pos = msg->len; @@ -1179,11 +1171,11 @@ static void xiic_start_send(struct xiic_i2c *i2c) /* Clear any pending Tx empty, Tx Error and then enable them */ xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK | ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? XIIC_INTR_TX_HALF_MASK : 0)); xiic_fill_tx_fifo(i2c); + xiic_clear_en_bnb(i2c); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty @@ -1225,8 +1217,9 @@ static void xiic_start_send(struct xiic_i2c *i2c) /* Clear any pending Tx empty, Tx Error and then enable them */ xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | - XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK); + XIIC_INTR_TX_ERROR_MASK); + + xiic_clear_en_bnb(i2c); } i2c->prev_msg_tx = true; -- 2.43.0