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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LY0PR12MB727857.namprd12.prod.outlook.com (2603:10b6:408:3ba::5) by CY8PR12MB7416.namprd12.prod.outlook.com (2603:10b6:930:5c::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.23; Tue, 13 Oct 2026 07:02:10 +0000 Received: from LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522]) by LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522%5]) with mapi id 15.21.0496.021; Tue, 13 Oct 2026 07:02:09 +0000 From: Srirangan Madhavan To: mark.rutland@arm.com, lpieralisi@kernel.org, sudeep.holla@kernel.org, conor@kernel.org, jic23@kernel.org Cc: catalin.marinas@arm.com, will@kernel.org, andre.przywara@arm.com, aneesh.kumar@kernel.org, Souvik.Chakravarty@arm.com, treding@nvidia.com, jonathanh@nvidia.com, bence.csokas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Srirangan Madhavan Subject: [PATCH v4 0/2] Add SMCCC cache clean/invalidate provider Date: Tue, 13 Oct 2026 07:02:03 +0000 Message-ID: <20261013070205.3566865-1-smadhavan@nvidia.com> X-Mailer: git-send-email 2.43.0 Content-Type: text/plain; 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Per DEN0028, this interface targets systems where a Normal Cacheable memory region can be modified in ways that are not handled by usual PE coherency mechanisms, and where VA-based CMOs may be too slow or insufficient for large ranges and/or system-cache implementations. Representative use cases include device-backed memory state transitions where stale CPU/system cache lines must be invalidated reliably (for example secure erase, reset/offline flows, and dynamic memory reconfiguration). Patch 1 introduces the Arm SMCCC cache clean/invalidate function IDs and transient return codes needed by callers [1]. Patch 2 adds a cache maintenance provider that: - registers the interface attributes function as an SMCCC device - binds to the service through the SMCCC bus - registers with the generic cache coherency framework used by cpu_cache_invalidate_memregion() - handles transient BUSY/RATE_LIMITED responses with bounded retries This patch set does not add a software fallback path; when firmware does not implement the SMCCC cache maintenance interface, the SMCCC device is not registered and existing behavior is preserved. The series is based on the current SMCCC bus topic branch queued for v7.4 [3]. References: [1] https://developer.arm.com/documentation/den0028/h [2] https://lore.kernel.org/linux-cxl/20260902072804.665639-1-smadhavan@nvidia.com/ [3] https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/smccc-bus DEN0028 v1.7 has since been confirmed as stable. Testing: - With corresponding TF-A support enabled, exercised the cache operation path through CXL Reset [2] and verified that it invokes the SMCCC call and completes the cache flush successfully. - ARM64 defconfig with CONFIG_CACHEMAINT_FOR_HOTPLUG=y and CONFIG_ARM_SMCCC_CACHE=y - W=1 build of drivers/cache/arm_smccc_cache.o - W=1 build of the ARM64 Image Changes since v3: - Rebased onto the current SMCCC bus topic branch queued for v7.4. - Converted the provider to an SMCCC bus driver and registered the attributes function as an SMCCC device. - Added an explicit DEN0028 v1.7 reference to the provider source and patch 2 commit message. - Dropped the unused tools/include copy of the new definitions. - Replaced the catch-all linux/kernel.h include with the specific headers used by the provider. - Added Reviewed-by tags for patch 1 from Bence and Andre. - Dropped the review tags from patch 2 because the SMCCC bus conversion changed its discovery and initialization paths after the rebase. Srirangan Madhavan (2): arm64: smccc: add cache clean/invalidate IDs and return codes cache: add SMCCC-backed cache invalidate provider drivers/cache/Kconfig | 11 +++ drivers/cache/Makefile | 2 + drivers/cache/arm_smccc_cache.c | 161 ++++++++++++++++++++++++++++++++ drivers/firmware/smccc/smccc.c | 5 + include/linux/arm-smccc.h | 21 ++++- 5 files changed, 198 insertions(+), 2 deletions(-) create mode 100644 drivers/cache/arm_smccc_cache.c base-commit: c6e78a4080a3b310a9f61db778d6dee7bc646cb7 -- 2.43.0