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Petersen" , Sai Krishna Potthuri , Ajay Neeli , Manivannan Sadhasivam , Pedro Sousa , Hannes Reinicke , Joao Pinto Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, clizzi@redhat.com, aruizrui@redhat.com, eballetb@redhat.com, echanude@redhat.com Subject: [PATCH v8 10/12] arm64: dts: freescale: s32n79: Add UFS host controller Date: Tue, 13 Oct 2026 12:30:01 +0200 Message-ID: <20261013103003.373156-11-larisa.grigore@oss.nxp.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261013103003.373156-1-larisa.grigore@oss.nxp.com> References: <20261013103003.373156-1-larisa.grigore@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR0P281CA0052.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:48::20) To GV2PR04MB12558.eurprd04.prod.outlook.com (2603:10a6:150:368::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12558:EE_|VI1PR04MB7133:EE_ X-MS-Office365-Filtering-Correlation-Id: 46fce847-29af-4ffd-cd0f-08df29150a49 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|23010399003|7416014|1800799024|376014|366016|22082099003|10067099003|18002099003|921020|11063799006|261009223027099003|56012099006; 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The controller remains disabled by default and is enabled by board dts files as needed. Signed-off-by: Larisa Grigore --- arch/arm64/boot/dts/freescale/s32n79.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi index 94ab58783fdc..c74264a3e4b1 100644 --- a/arch/arm64/boot/dts/freescale/s32n79.dtsi +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi @@ -100,6 +100,30 @@ uart7: serial@4aa40000 { status = "disabled"; }; + ufshc: ufs@4ac80000 { + compatible = "nxp,s32n79-ufshc"; + reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>; + reg-names = "ufshc", "scm"; + interrupt-parent = <&irqsteer_coss>; + interrupts = <211>; + clocks = <&clks 0x92>; + clock-names = "core"; + operating-points-v2 = <&ufs_opp_table>; + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* + * The core reference clock runs at a fixed rate + * set by its parent, so no scaling is performed. + */ + opp-0 { + opp-hz = /bits/ 64 <0>; + }; + }; + }; + irqsteer_coss: interrupt-controller@4ed00000 { compatible = "nxp,s32n79-irqsteer"; reg = <0x4ed00000 0x10000>; -- 2.43.0