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Tue, 13 Oct 2026 08:19:51 -0700 (PDT) Received: from buffalo-ssd.taila54753.ts.net ([240b:253:4760:f400:1ebf:ceff:fe7f:5e0b]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd3da04596dsm5759888a12.29.2026.10.13.08.19.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 08:19:50 -0700 (PDT) From: Akari Tsuyukusa To: Brian Masney , Jerome Brunet , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Chen-Yu Tsai , Bartosz Golaszewski , Kees Cook , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Danilo Krummrich , Nicolas Frattaroli , Bjorn Helgaas , Takashi Sakamoto , Haotian Zhang , Miles Chen , Sam Shih , Daniel Golle , Chun-Jie Chen , Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), Akari Tsuyukusa Subject: [PATCH v2 19/35] clk: mediatek: mt6779: Switch to common probe/remove helpers Date: Wed, 14 Oct 2026 00:17:18 +0900 Message-ID: <20261013151734.3177690-20-akkun11.open@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261013151734.3177690-1-akkun11.open@gmail.com> References: <20261013151734.3177690-1-akkun11.open@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261013_161953_947117_A6390080 X-CRM114-Status: GOOD ( 18.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MT6779 apmixedsys driver used a custom probe to register PLLs. With PLL registration now supported by the common helpers, it can use mtk_clk_simple_probe() and mtk_clk_simple_remove(). Consolidate the apmixedsys, topckgen, and infracfg match entries under a single platform driver, using struct mtk_clk_desc for the clock configurations. Replace the custom arch_initcall() registration with module_platform_driver(). Signed-off-by: Akari Tsuyukusa --- Changes in v2: - Improvement of commit messages --- drivers/clk/mediatek/clk-mt6779.c | 124 ++++++------------------------ 1 file changed, 22 insertions(+), 102 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 4b9dcb910b03..a806789ae27c 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -808,7 +808,7 @@ static const char * const i2s5_m_ck_parents[] = { "aud_2_sel" }; -static const struct mtk_composite top_aud_muxes[] = { +static const struct mtk_composite top_aud_muxes_divs[] = { MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x320, 8, 1), MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, @@ -821,9 +821,7 @@ static const struct mtk_composite top_aud_muxes[] = { 0x320, 12, 1), MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents, 0x328, 20, 1), -}; -static struct mtk_composite top_aud_divs[] = { DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel", 0x320, 2, 0x324, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel", @@ -1211,125 +1209,47 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4), }; -static int clk_mt6779_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static int clk_mt6779_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - - mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt6779_clk_lock, clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_muxes, - ARRAY_SIZE(top_aud_muxes), base, - &mt6779_clk_lock, clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_divs, - ARRAY_SIZE(top_aud_divs), base, - &mt6779_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static const struct of_device_id of_match_clk_mt6779[] = { - { - .compatible = "mediatek,mt6779-apmixed", - .data = clk_mt6779_apmixed_probe, - }, { - .compatible = "mediatek,mt6779-topckgen", - .data = clk_mt6779_top_probe, - }, { - /* sentinel */ - } +static const struct mtk_clk_desc apmixed_desc = { + .clks = apmixed_clks, + .num_clks = ARRAY_SIZE(apmixed_clks), + .plls = plls, + .num_plls = ARRAY_SIZE(plls), }; -static int clk_mt6779_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe = of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r = clk_probe(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_muxes, + .num_mux_clks = ARRAY_SIZE(top_muxes), + .composite_clks = top_aud_muxes_divs, + .num_composite_clks = ARRAY_SIZE(top_aud_muxes_divs), + .clk_lock = &mt6779_clk_lock, +}; static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), }; -static const struct of_device_id of_match_clk_mt6779_infra[] = { +static const struct of_device_id of_match_clk_mt6779[] = { + { .compatible = "mediatek,mt6779-apmixed", .data = &apmixed_desc }, + { .compatible = "mediatek,mt6779-topckgen", .data = &topck_desc }, { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt6779); -static struct platform_driver clk_mt6779_infra_drv = { +static struct platform_driver clk_mt6779_drv = { .probe = mtk_clk_simple_probe, .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt6779-infra", - .of_match_table = of_match_clk_mt6779_infra, - }, -}; - -static struct platform_driver clk_mt6779_drv = { - .probe = clk_mt6779_probe, .driver = { .name = "clk-mt6779", .of_match_table = of_match_clk_mt6779, }, }; - -static int __init clk_mt6779_init(void) -{ - int ret = platform_driver_register(&clk_mt6779_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt6779_infra_drv); -} - -arch_initcall(clk_mt6779_init); +module_platform_driver(clk_mt6779_drv); MODULE_DESCRIPTION("MediaTek MT6779 main clocks driver"); MODULE_LICENSE("GPL"); -- 2.56.0