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[2a02:3100:a189:2701:8c58:155a:279:7389]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1b481b7f8sm5237345e9.3.2026.10.13.13.32.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 13 Oct 2026 13:32:04 -0700 (PDT) From: Karl Mehltretter To: Russell King , Miguel Ojeda Cc: Karl Mehltretter , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?UTF-8?q?Onur=20=C3=96zkan?= , Arnd Bergmann , Linus Walleij , Christian Schrefl , Bradley Morgan , "Paul E . McKenney" , Peter Zijlstra , FUJITA Tomonori , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] ARM: rust: Enable Rust support for ARMv5TE Date: Tue, 13 Oct 2026 22:31:38 +0200 Message-Id: <20261013203140.31741-5-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261013203140.31741-1-kmehltretter@gmail.com> References: <20261013203140.31741-1-kmehltretter@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261013_133210_963353_BF24CA3E X-CRM114-Status: GOOD ( 16.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The arm-unknown-linux-gnueabi target enables +v6 and emits instructions that ARMv5 does not support. -Ctarget-cpu=arm926ej-s does not remove +v6, while -Ctarget-feature=-v6 produces an unstable-feature warning. Use armv5te-unknown-linux-gnueabi for CPU_32v5. It uses the Linux soft-float EABI, requires strict alignment and declares 32-bit atomics. Select it alongside -march so Rust and C follow the same CPU selection. Kernels containing ARMv4 or ARMv4T CPUs remain excluded. CPU_32v5 also covers ARM1020, for which C already uses -march=armv5te. The kernel crate implements atomics through C helpers. The preceding patch supplies the missing 2-byte xchg() on pre-ARMv6 CPUs. core::sync::atomic remains unusable because LLVM lowers its operations to __sync_* libcalls that the kernel does not provide. No in-tree code uses them. Tested the Rust samples, KUnit suites and doctests in QEMU versatilepb with versatile_defconfig and on a Microchip SAM9X75 Curiosity board. Link: https://lore.kernel.org/rust-for-linux/CACRpkdYF0sVB2-qgy=GzETSR3+2sagVQPGdunDQDJrn8KqJorA@mail.gmail.com/ Link: https://lore.kernel.org/rust-for-linux/b13d37bd-ec68-4713-94e5-e9ed4d6a6354@gmail.com/ Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Documentation/rust/arch-support.rst | 2 +- arch/arm/Kconfig | 8 +++++++- arch/arm/Makefile | 7 ++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst index bdc42a24bf30..d6d1bef44c8f 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -15,7 +15,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`` file. ============= ================ ============================================== Architecture Level of support Constraints ============= ================ ============================================== -``arm`` Maintained ARMv6K and ARMv7, Little Endian only. +``arm`` Maintained ARMv5TE, ARMv6K and ARMv7, Little Endian only. ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- ``riscv`` Maintained ``riscv64`` and LLVM/Clang only. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5816f28783a..9275a85f95e9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -138,7 +138,7 @@ config ARM select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ - select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v6K && !CPU_V6 && !KASAN + select HAVE_RUST if CPU_LITTLE_ENDIAN && ARM_RUST_TARGET && !KASAN select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 @@ -172,6 +172,12 @@ config ARM Europe. There is an ARM Linux project with a web page at . +# The CPU selections for which rustc has a matching target +config ARM_RUST_TARGET + def_bool y + depends on (CPU_32v6K && !CPU_V6) || \ + (CPU_32v5 && !CPU_32v4T && !CPU_32v4) + config ARM_HAS_GROUP_RELOCS def_bool !COMPILE_TEST help diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 573813ef5e77..168779e9e93d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -73,6 +73,11 @@ arch-$(CONFIG_CPU_32v4T) :=-march=armv4t arch-$(CONFIG_CPU_32v4) :=-march=armv4 arch-$(CONFIG_CPU_32v3) :=-march=armv3m +# The rustc target fixes the instruction set. -Ctarget-cpu cannot remove +# the +v6 of the generic target, so older CPUs need their own target. +rust-target-y :=arm-unknown-linux-gnueabi +rust-target-$(CONFIG_CPU_32v5) :=armv5te-unknown-linux-gnueabi + # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. @@ -150,7 +155,7 @@ endif KBUILD_CPPFLAGS +=$(cpp-y) KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) -Wa,$(arch-y) $(tune-y) -include $(srctree)/arch/arm/include/asm/unified.h -msoft-float -KBUILD_RUSTFLAGS += --target=arm-unknown-linux-gnueabi +KBUILD_RUSTFLAGS += --target=$(rust-target-y) CHECKFLAGS += -D__arm__ -- 2.39.5 (Apple Git-154)