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[92.76.89.226]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c3eda5297b0sm96080666b.63.2026.10.15.01.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 01:11:50 -0700 (PDT) From: Thilo Zirnstein To: michal.simek@amd.com, andi.shyti@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Thilo Zirnstein Subject: [PATCH v2 1/1] i2c: i2c-xiic: fix clearing of bnb irq Date: Thu, 15 Oct 2026 10:11:27 +0200 Message-ID: <20261015081127.1566244-2-thi.zirnstein@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261015081127.1566244-1-thi.zirnstein@gmail.com> References: <20261015081127.1566244-1-thi.zirnstein@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261015_011152_765592_BEAACBC7 X-CRM114-Status: GOOD ( 18.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a function for clearing the bnb bit, It waits for all preconditions before clearing the bnb bit or times out. Tested on Zynqmp dev board with some custom logic. Tested-by: Thilo Zirnstein Signed-off-by: Thilo Zirnstein --- drivers/i2c/busses/i2c-xiic.c | 42 +++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 5e397a7e63f6..da9cedb86f94 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -230,7 +230,9 @@ static const struct timing_regs timing_reg_values[] = { #define XIIC_RESET_MASK 0xAUL -#define XIIC_PM_TIMEOUT 1000 /* ms */ +#define XIIC_PM_TIMEOUT 1000 /* ms */ +/* timeout waiting for bus busy */ +#define XIIC_BB_TIMEOUT (msecs_to_jiffies(1)) /* timeout waiting for the controller to respond */ #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) /* timeout waiting for the controller finish transfers */ @@ -392,6 +394,30 @@ static int xiic_wait_tx_empty(struct xiic_i2c *i2c) return 0; } +static int xiic_clear_en_bnb(struct xiic_i2c *i2c) +{ + u8 sr = 0, isr = 0; + unsigned long timeout; + + timeout = jiffies + XIIC_BB_TIMEOUT; + for (isr = xiic_getreg8(i2c, XIIC_IISR_OFFSET); + (isr & XIIC_INTR_BNB_MASK); + isr = xiic_getreg8(i2c, XIIC_IISR_OFFSET)) { + + sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); + if (sr & XIIC_SR_BUS_BUSY_MASK) + xiic_setreg8(i2c, XIIC_IISR_OFFSET, XIIC_INTR_BNB_MASK); + + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Failed to clear bnb\n"); + return -ETIMEDOUT; + } + } + + xiic_irq_en(i2c, XIIC_INTR_BNB_MASK); + return 0; +} + /** * xiic_setclk - Sets the configured clock rate * @i2c: Pointer to the xiic device structure @@ -881,9 +907,6 @@ static irqreturn_t xiic_process(int irq, void *dev_id) } if (pend & XIIC_INTR_BNB_MASK) { - /* IIC bus has transitioned to not busy */ - clr |= XIIC_INTR_BNB_MASK; - /* The bus is not busy, disable BusNotBusy interrupt */ xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); @@ -1028,7 +1051,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val); - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + xiic_clear_en_bnb(i2c); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty @@ -1095,7 +1118,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c) if (i2c->nmsgs == 1) /* very last, enable bus not busy as well */ - xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); + xiic_clear_en_bnb(i2c); /* the message is tx:ed */ i2c->tx_pos = msg->len; @@ -1179,11 +1202,11 @@ static void xiic_start_send(struct xiic_i2c *i2c) /* Clear any pending Tx empty, Tx Error and then enable them */ xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK | ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? XIIC_INTR_TX_HALF_MASK : 0)); xiic_fill_tx_fifo(i2c); + xiic_clear_en_bnb(i2c); } else { /* * If previous message is Tx, make sure that Tx FIFO is empty @@ -1225,8 +1248,9 @@ static void xiic_start_send(struct xiic_i2c *i2c) /* Clear any pending Tx empty, Tx Error and then enable them */ xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | - XIIC_INTR_TX_ERROR_MASK | - XIIC_INTR_BNB_MASK); + XIIC_INTR_TX_ERROR_MASK); + + xiic_clear_en_bnb(i2c); } i2c->prev_msg_tx = true; -- 2.43.0