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From: Sascha Bischoff <sascha.bischoff@arm.com>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	kvm@vger.kernel.org
Cc: maz@kernel.org, oupton@kernel.org, fuad.tabba@linux.dev,
	joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com,
	yuzenghui@huawei.com
Subject: [PATCH 0/2] KVM: arm64: Reject mismatched GICv3 ITS/VGIC models
Date: Fri, 16 Oct 2026 16:22:22 +0100	[thread overview]
Message-ID: <20261016152225.898761-1-sascha.bischoff@arm.com> (raw)

On a GICv5 host with legacy GICv3 support, KVM exposes both VGIC
models to userspace. A VM can create a GICv3 ITS alongside a GICv5
VGIC, because neither creation path checks the model of the other
device. The ITS sets has_its, but a GICv5 VM cannot use a GICv3 ITS
for MSI translation. Creating the ITS before the VGIC also lets
userspace select an incompatible VGIC model later.

Record the VGIC model required by a GICv3 ITS and reject incompatible
device creation in either order. The second patch tests both orderings,
skipping the test if the host does not offer a GICv3 ITS.

This series is based on kvmarm/next-7.4+fixes-7.3-2.

Sascha

Sascha Bischoff (2):
  KVM: arm64: vgic: Require matching VGIC model for GICv3 ITS
  KVM: selftests: Reject GICv3 ITS with a GICv5 VGIC

 arch/arm64/kvm/vgic/vgic-init.c             |  5 ++++
 arch/arm64/kvm/vgic/vgic-its.c              |  9 ++++++
 include/kvm/arm_vgic.h                      |  2 ++
 tools/testing/selftests/kvm/arm64/vgic_v5.c | 32 +++++++++++++++++++++
 4 files changed, 48 insertions(+)


base-commit: 678f16b6e4767096aa3e3e6eef60e981b3f61e12
-- 
2.34.1



             reply	other threads:[~2026-10-16 15:22 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16 15:22 Sascha Bischoff [this message]
2026-10-16 15:22 ` [PATCH 1/2] KVM: arm64: vgic: Require matching VGIC model for GICv3 ITS Sascha Bischoff
2026-10-17 11:51   ` Marc Zyngier
2026-10-19 13:24     ` Sascha Bischoff
2026-10-16 15:22 ` [PATCH 2/2] KVM: selftests: Reject GICv3 ITS with a GICv5 VGIC Sascha Bischoff

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