From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA3B9CCF2C2 for ; Fri, 16 Oct 2026 19:34:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FZL8PfkThKX2iAppqn/43ztzq+aJ7s8ZsROCzA6oW9I=; b=lYdDYpreHcOrgOdmPpBTsDMBJb W/HBR8AdGUAldjgrV3wRcG+VIPGZbouWh9m9j4NpR0iOCZQAZLQWrYGzsDv2DwdsCOMcPzgYMmjxs gx5JN21xK+35xR4DFlHGRVdf6NUDqHCM0cSgODGwo7X7llJYSy62eLocyl16EDNjzOegt7vR8kxFw qaD1giF6NVgyAW7zBfm6IFNBJ2lq8yvpjLX5JrZxhDrdTvRlBCcPqUePIADKQ+fPWBhe5LZcI37fa ocLBpGBJxAS3XNn28lvqJBjGNd9IFz8vz+MzEtNVQg7PXz25l9I87Mmt3hqdgc4cCcJUuRPaGAxSY wdGWdG6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xHngr-00000003uKI-3KSR; Fri, 16 Oct 2026 19:34:05 +0000 Received: from mx.nabladev.com ([178.251.229.89]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1xHngo-00000003uJK-2pnL for linux-arm-kernel@lists.infradead.org; Fri, 16 Oct 2026 19:34:04 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7C506109A06; Fri, 16 Oct 2026 21:33:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1792179236; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=FZL8PfkThKX2iAppqn/43ztzq+aJ7s8ZsROCzA6oW9I=; b=CKdELMX1Ka+hgZceWrxbziJUGxXJLD1NH7LslvieXtRG38CvVFUHQ0v6FKg5oFgB9qybbL S8rArappOpt7gvdGhhBEXhV/rk44WloddUG+nv1Ujw4Ak4ocCCK9jdvDxME9vqvCi9KA6L u9Mkoukrpd7mOSMyP8iwXdsUgshQdlfXHZ8ZaaWYkJgvC8F6EHILEB5nGqqwN/fjSNT10D v1SS14O8ldYPfw612YWryLyCVtn63NoIwxWMOkfI7aV6OiRj/VLVpJpKgT7R7RE91pNsYY oZb+zaB0Jnmgj3PHw8RHNd/YZdn0iS0u8DgGFCPKPpMDgFuo7aTs4M1YYalfiA== From: Marek Vasut To: netdev@vger.kernel.org Cc: Marek Vasut , Vladimir Oltean , "Christophe Leroy (CS GROUP)" , "David S. Miller" , Andrew Lunn , Clark Wang , Claudiu Manoil , Conor Dooley , Eric Dumazet , Frank Li , Jakub Kicinski , Krzysztof Kozlowski , Paolo Abeni , Rob Herring , UNGLinuxDriver@microchip.com, Wei Fang , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [net-next,PATCH 2/2] enetc: Make eMDIO MDC rate configurable from DT Date: Fri, 16 Oct 2026 21:32:01 +0200 Message-ID: <20261016193344.115518-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261016193344.115518-1-marex@nabladev.com> References: <20261016193344.115518-1-marex@nabladev.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261016_123403_009774_DAE7048C X-CRM114-Status: GOOD ( 21.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current eMDIO MDC rate is hard-coded in the drivers which use the eMDIO MDC, this is not flexible for various deployments of SoCs which use the eMDIO interface, for example i.MX95 B0 MDC clock is currently set to 644 kHz. Introduce enetc_mdio_priv .mdc_div field which contains the divider used for MDC clock and pass it around, including into functions which configure the MDC clock. This way, drivers which use the eMDIO can set the divider as needed. Introduce enetc_mdio_update_mdc_div() function which calculates the divider from upstream clock and clock-frequency DT property, both of which are optional to retain compatibility with older DTs. This is modeled according to xgmac_mdio_set_mdc_freq(). Suggested-by: Vladimir Oltean Signed-off-by: Marek Vasut --- Cc: "Christophe Leroy (CS GROUP)" Cc: "David S. Miller" Cc: Andrew Lunn Cc: Clark Wang Cc: Claudiu Manoil Cc: Conor Dooley Cc: Eric Dumazet Cc: Frank Li Cc: Jakub Kicinski Cc: Krzysztof Kozlowski Cc: Paolo Abeni Cc: Rob Herring Cc: UNGLinuxDriver@microchip.com Cc: Vladimir Oltean Cc: Wei Fang Cc: devicetree@vger.kernel.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: netdev@vger.kernel.org --- NOTE: I could only test i.MX95 , I could not test LS or Felix --- drivers/net/dsa/ocelot/felix_vsc9959.c | 5 +++ .../net/ethernet/freescale/enetc/enetc_mdio.c | 39 ++++++++++++++++--- .../ethernet/freescale/enetc/enetc_pci_mdio.c | 5 +++ .../freescale/enetc/enetc_pf_common.c | 10 +++++ include/linux/fsl/enetc_mdio.h | 6 +++ 5 files changed, 59 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 8387dd208adb9..dbeec1b229325 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -1008,8 +1008,13 @@ static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) * starting with the proper offset. */ mdio_priv->mdio_base = 0; + mdio_priv->mdc_div = ENETC_MDIO_DEFAULT_DIVIDER; snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); + rc = enetc_mdio_update_mdc_div(bus); + if (rc) + return rc; + /* Needed in order to initialize the bus mutex lock */ rc = mdiobus_register(bus); if (rc < 0) { diff --git a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c index 998aaa394e9c4..93d61c2f1464f 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* Copyright 2019 NXP */ +#include #include #include #include @@ -22,9 +23,9 @@ /* external MDIO only - driven on neg MDC edge */ #define MDIO_CFG_NEG BIT(23) -#define ENETC_EMDIO_CFG \ +#define ENETC_EMDIO_CFG(mdc_div) \ (MDIO_CFG_HOLD(2) | \ - MDIO_CFG_CLKDIV(258) | \ + MDIO_CFG_CLKDIV(mdc_div) | \ MDIO_CFG_NEG) #define MDIO_CTL_DEV_ADDR(x) ((x) & 0x1f) @@ -63,7 +64,7 @@ int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 dev_addr; int ret; - mdio_cfg = ENETC_EMDIO_CFG; + mdio_cfg = ENETC_EMDIO_CFG(mdio_priv->mdc_div); dev_addr = regnum & 0x1f; mdio_cfg &= ~MDIO_CFG_ENC45; @@ -95,7 +96,7 @@ int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, u32 mdio_ctl, mdio_cfg; int ret; - mdio_cfg = ENETC_EMDIO_CFG; + mdio_cfg = ENETC_EMDIO_CFG(mdio_priv->mdc_div); mdio_cfg |= MDIO_CFG_ENC45; enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); @@ -133,7 +134,7 @@ int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) u16 dev_addr, value; int ret; - mdio_cfg = ENETC_EMDIO_CFG; + mdio_cfg = ENETC_EMDIO_CFG(mdio_priv->mdc_div); dev_addr = regnum & 0x1f; mdio_cfg &= ~MDIO_CFG_ENC45; @@ -176,7 +177,7 @@ int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, u16 value; int ret; - mdio_cfg = ENETC_EMDIO_CFG; + mdio_cfg = ENETC_EMDIO_CFG(mdio_priv->mdc_div); mdio_cfg |= MDIO_CFG_ENC45; enetc_mdio_wr(mdio_priv, ENETC_MDIO_CFG, mdio_cfg); @@ -231,6 +232,32 @@ struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) } EXPORT_SYMBOL_GPL(enetc_hw_alloc); +int enetc_mdio_update_mdc_div(struct mii_bus *bus) +{ + struct enetc_mdio_priv *mdio_priv = bus->priv; + struct device *dev = bus->parent; + struct clk *enet_clk; + u32 div, mdc_freq; + + if (device_property_read_u32(dev, "clock-frequency", &mdc_freq)) + return 0; + + enet_clk = devm_clk_get(dev, NULL); + if (IS_ERR(enet_clk)) + return dev_err_probe(dev, PTR_ERR(enet_clk), + "Input clock unknown, not changing MDC frequency\n"); + + div = ((clk_get_rate(enet_clk) / mdc_freq) - 1) / 4; + if (div < 5 || div > 0x1ff) + return dev_err_probe(dev, -EINVAL, + "Requested MDC frequency is out of range, ignoring\n"); + + mdio_priv->mdc_div = div; + + return 0; +} +EXPORT_SYMBOL_GPL(enetc_mdio_update_mdc_div); + /* Lock for MDIO access errata on LS1028A */ DEFINE_RWLOCK(enetc_mdio_lock); EXPORT_SYMBOL_GPL(enetc_mdio_lock); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c b/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c index e108cac8288d3..4ff182d7d21ec 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c @@ -71,8 +71,13 @@ static int enetc_pci_mdio_probe(struct pci_dev *pdev, mdio_priv = bus->priv; mdio_priv->hw = hw; mdio_priv->mdio_base = ENETC_EMDIO_BASE; + mdio_priv->mdc_div = ENETC_MDIO_DEFAULT_DIVIDER; snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + err = enetc_mdio_update_mdc_div(bus); + if (err) + return err; + pcie_flr(pdev); err = pci_enable_device_mem(pdev); if (err) { diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c b/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c index 8206884294a47..adba3fdea32dc 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf_common.c @@ -300,6 +300,7 @@ static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np) bus->parent = dev; mdio_priv = bus->priv; mdio_priv->hw = &pf->si->hw; + mdio_priv->mdc_div = ENETC_MDIO_DEFAULT_DIVIDER; if (is_enetc_rev1(pf->si)) mdio_priv->mdio_base = ENETC_EMDIO_BASE; @@ -308,6 +309,10 @@ static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np) snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + err = enetc_mdio_update_mdc_div(bus); + if (err) + return err; + err = of_mdiobus_register(bus, np); if (err) return dev_err_probe(dev, err, "cannot register MDIO bus\n"); @@ -350,6 +355,7 @@ static int enetc_imdio_create(struct enetc_pf *pf) bus->phy_mask = ~0; mdio_priv = bus->priv; mdio_priv->hw = &pf->si->hw; + mdio_priv->mdc_div = ENETC_MDIO_DEFAULT_DIVIDER; if (is_enetc_rev1(pf->si)) mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE; @@ -358,6 +364,10 @@ static int enetc_imdio_create(struct enetc_pf *pf) snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); + err = enetc_mdio_update_mdc_div(bus); + if (err) + return err; + err = mdiobus_register(bus); if (err) { dev_err(dev, "cannot register internal MDIO bus (%d)\n", err); diff --git a/include/linux/fsl/enetc_mdio.h b/include/linux/fsl/enetc_mdio.h index 623ccfcbf39c3..13eb6939efe29 100644 --- a/include/linux/fsl/enetc_mdio.h +++ b/include/linux/fsl/enetc_mdio.h @@ -6,6 +6,8 @@ #include +#define ENETC_MDIO_DEFAULT_DIVIDER 258 + /* PCS registers */ #define ENETC_PCS_LINK_TIMER1 0x12 #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 @@ -33,6 +35,7 @@ struct enetc_hw; struct enetc_mdio_priv { struct enetc_hw *hw; int mdio_base; + int mdc_div; }; #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO) @@ -44,6 +47,7 @@ int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int devad, int regnum); int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int devad, int regnum, u16 value); struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs); +int enetc_mdio_update_mdc_div(struct mii_bus *bus); #else @@ -62,6 +66,8 @@ static inline int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, static inline struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) { return ERR_PTR(-EINVAL); } +static inline int enetc_mdio_update_mdc_div(struct mii_bus *bus) +{ return -EINVAL; } #endif -- 2.53.0