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Signed-off-by: James Tai Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- drivers/irqchip/Kconfig | 12 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-rtd1625.c | 261 ++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-rtd1625.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 2598f6a82cc2..c97c32f3f0a8 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -320,6 +320,18 @@ config REALTEK_RTD1619B_INTC If unsure, say N. +config REALTEK_RTD1625_INTC + tristate "Realtek RTD1625 interrupt controller" + depends on ARCH_REALTEK || COMPILE_TEST + select REALTEK_DHC_INTC + help + Enable support for the Realtek RTD1625 SoC interrupt controller. + The RTD1625 SoC features complex interrupt routing with multiple + interrupt banks. For example, its misc interrupt controller region + contains two register sets. + + If unsure, say N. + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index acc515fc6f9a..6fec774cfb2c 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_REALTEK_DHC_INTC) += irq-realtek-intc-common.o obj-$(CONFIG_REALTEK_RTD1319_INTC) += irq-realtek-rtd1319.o obj-$(CONFIG_REALTEK_RTD1319D_INTC) += irq-realtek-rtd1319d.o obj-$(CONFIG_REALTEK_RTD1619B_INTC) += irq-realtek-rtd1619b.o +obj-$(CONFIG_REALTEK_RTD1625_INTC) += irq-realtek-rtd1625.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-rtd1625.c b/drivers/irqchip/irq-realtek-rtd1625.c new file mode 100644 index 000000000000..4cca66c8ff70 --- /dev/null +++ b/drivers/irqchip/irq-realtek-rtd1625.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Realtek RTD1625 interrupt controller driver + * + * Copyright (c) 2026 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include "irq-realtek-intc-common.h" + +#define ISO_NORMAL_MASK 0xfffe0ff6 +#define ISO_UART9_MASK 0x00000008 +#define ISO_RTC_MASK 0x0001f000 +#define ISOM_NORMAL_MASK 0x00000037 +#define MISC_NORMAL_MASK 0xfffffffe +#define MISC2_NORMAL_MASK 0xfffffff8 +#define MISC2_UART1_MASK 0x00000002 +#define MISC2_UART2_MASK 0x00000004 + +#define ISO_ISR_EN_OFFSET 0x40 +#define ISO_ISR_OFFSET 0 +#define ISOM_ISR_EN_OFFSET 0x10 +#define ISOM_ISR_OFFSET 0 +#define MISC_ISR_EN_OFFSET 0x80 +#define MISC_ISR_OFFSET 0xc +#define MISC2_ISR_EN_OFFSET 0x88 +#define MISC2_ISR_OFFSET 0x4 + +enum rtd1625_iso_isr_bits { + RTD1625_ISO_ISR_UR0_SHIFT = 2, + RTD1625_ISO_ISR_UR9_SHIFT = 3, + RTD1625_ISO_ISR_SPI0_SHIFT = 4, + RTD1625_ISO_ISR_SPI1_SHIFT = 5, + RTD1625_ISO_ISR_SPI2_SHIFT = 6, + RTD1625_ISO_ISR_I2C0_SHIFT = 8, + RTD1625_ISO_ISR_I2C7_SHIFT = 10, + RTD1625_ISO_ISR_I2C1_SHIFT = 11, + RTD1625_ISO_ISR_DRTC_HSEC_SHIFT = 12, + RTD1625_ISO_ISR_DRTC_MIN_SHIFT = 13, + RTD1625_ISO_ISR_DRTC_HOUR_SHIFT = 14, + RTD1625_ISO_ISR_DRTC_DATE_SHIFT = 15, + RTD1625_ISO_ISR_DRTC_ALARM_SHIFT = 16, + RTD1625_ISO_ISR_VFD_SHIFT = 17, + RTD1625_ISO_ISR_GPIOA_SHIFT = 19, + RTD1625_ISO_ISR_GPIODA_SHIFT = 20, + RTD1625_ISO_ISR_LSADC0_SHIFT = 21, + RTD1625_ISO_ISR_LSADC1_SHIFT = 22, + RTD1625_ISO_ISR_PORB_HV_CEN_SHIFT = 28, + RTD1625_ISO_ISR_PORB_DV_CEN_SHIFT = 29, + RTD1625_ISO_ISR_PORB_AV_CEN_SHIFT = 30, + RTD1625_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1625_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1625_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1625_ISO_ISR_UR9_SHIFT] = BIT(3), + [RTD1625_ISO_ISR_SPI0_SHIFT] = BIT(4), + [RTD1625_ISO_ISR_SPI1_SHIFT] = BIT(5), + [RTD1625_ISO_ISR_SPI2_SHIFT] = BIT(6), + [RTD1625_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1625_ISO_ISR_I2C7_SHIFT] = BIT(10), + [RTD1625_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1625_ISO_ISR_DRTC_HSEC_SHIFT] = BIT(12), + [RTD1625_ISO_ISR_DRTC_MIN_SHIFT] = BIT(13), + [RTD1625_ISO_ISR_DRTC_HOUR_SHIFT] = BIT(14), + [RTD1625_ISO_ISR_DRTC_DATE_SHIFT] = BIT(15), + [RTD1625_ISO_ISR_DRTC_ALARM_SHIFT] = BIT(16), + [RTD1625_ISO_ISR_VFD_SHIFT] = BIT(17), + [RTD1625_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1625_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1625_ISO_ISR_LSADC0_SHIFT] = BIT(21), + [RTD1625_ISO_ISR_LSADC1_SHIFT] = BIT(22), + [RTD1625_ISO_ISR_PORB_HV_CEN_SHIFT] = BIT(28), + [RTD1625_ISO_ISR_PORB_DV_CEN_SHIFT] = BIT(29), + [RTD1625_ISO_ISR_PORB_AV_CEN_SHIFT] = BIT(30), + [RTD1625_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1625_misc_isr_bits { + RTD1625_MISC_ISR_TC8_SHIFT = 1, + RTD1625_MISC_ISR_TC9_SHIFT = 2, + RTD1625_MISC_ISR_TC5_SHIFT = 4, + RTD1625_MISC_ISR_TC0_SHIFT = 6, + RTD1625_MISC_ISR_TC1_SHIFT = 7, + RTD1625_MISC_ISR_I2C5_SHIFT = 14, + RTD1625_MISC_ISR_I2C4_SHIFT = 15, + RTD1625_MISC_ISR_I2C6_SHIFT = 22, + RTD1625_MISC_ISR_I2C3_SHIFT = 23, + RTD1625_MISC_ISR_SC0_SHIFT = 24, + RTD1625_MISC_ISR_SC1_SHIFT = 25, + RTD1625_MISC_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1625_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1625_MISC_ISR_I2C6_SHIFT] = BIT(13), + [RTD1625_MISC_ISR_I2C5_SHIFT] = BIT(14), + [RTD1625_MISC_ISR_I2C4_SHIFT] = BIT(15), + [RTD1625_MISC_ISR_SC0_SHIFT] = BIT(24), + [RTD1625_MISC_ISR_SC1_SHIFT] = BIT(25), + [RTD1625_MISC_ISR_I2C3_SHIFT] = BIT(28), + [RTD1625_MISC_ISR_FAN_SHIFT] = BIT(29), +}; + +enum rtd1625_misc_isr2_bits { + RTD1625_MISC_ISR_UR1_SHIFT = 1, + RTD1625_MISC_ISR_UR2_SHIFT = 2, + RTD1625_MISC_ISR_UR3_SHIFT = 3, + RTD1625_MISC_ISR_UR4_SHIFT = 4, + RTD1625_MISC_ISR_UR5_SHIFT = 5, + RTD1625_MISC_ISR_UR6_SHIFT = 6, + RTD1625_MISC_ISR_UR7_SHIFT = 7, + RTD1625_MISC_ISR_UR8_SHIFT = 8, +}; + +static const u32 rtd1625_misc_isr2_to_scpu_int_en_mask[32] = { + [RTD1625_MISC_ISR_UR1_SHIFT] = BIT(0), + [RTD1625_MISC_ISR_UR2_SHIFT] = IRQ_ALWAYS_ENABLED, + [RTD1625_MISC_ISR_UR3_SHIFT] = BIT(4), + [RTD1625_MISC_ISR_UR4_SHIFT] = BIT(6), + [RTD1625_MISC_ISR_UR5_SHIFT] = BIT(8), + [RTD1625_MISC_ISR_UR6_SHIFT] = BIT(10), + [RTD1625_MISC_ISR_UR7_SHIFT] = BIT(12), + [RTD1625_MISC_ISR_UR8_SHIFT] = BIT(14), +}; + +enum rtd1625_isom_isr_bits { + RTD1625_ISOM_ISR_GPIOA_SHIFT = 0, + RTD1625_ISOM_ISR_GPIODA_SHIFT = 1, + RTD1625_ISOM_ISR_GPIO_LEVEL_SHIFT = 2, + RTD1625_ISOM_ISR_UR10_SHIFT = 4, + RTD1625_ISOM_ISR_IRDA_SHIFT = 5, +}; + +static const u32 rtd1625_isom_isr_to_scpu_int_en_mask[32] = { + [RTD1625_ISOM_ISR_GPIOA_SHIFT] = BIT(0), + [RTD1625_ISOM_ISR_GPIODA_SHIFT] = BIT(1), + [RTD1625_ISOM_ISR_GPIO_LEVEL_SHIFT] = BIT(2), + [RTD1625_ISOM_ISR_UR10_SHIFT] = BIT(4), + [RTD1625_ISOM_ISR_IRDA_SHIFT] = BIT(5), +}; + +static const struct realtek_intc_mask rtd1625_intc_iso_cfgs[] = { + { ISO_NORMAL_MASK, }, + { ISO_UART9_MASK, }, + { ISO_RTC_MASK, }, +}; + +static const struct realtek_intc_info rtd1625_intc_iso_info[] = { + { + .isr_offset = ISO_ISR_OFFSET, + .scpu_int_en_offset = ISO_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask = rtd1625_iso_isr_to_scpu_int_en_mask, + .subset_mask = rtd1625_intc_iso_cfgs, + .subset_num = ARRAY_SIZE(rtd1625_intc_iso_cfgs), + }, +}; + +static const struct realtek_intc_desc rtd1625_intc_iso_desc = { + .banks = rtd1625_intc_iso_info, + .bank_num = ARRAY_SIZE(rtd1625_intc_iso_info), + .shared_irq_mask = BIT(0), +}; + +static const struct realtek_intc_mask rtd1625_intc_isom_cfgs[] = { + { ISOM_NORMAL_MASK, }, +}; + +static const struct realtek_intc_info rtd1625_intc_isom_info[] = { + { + .isr_offset = ISOM_ISR_OFFSET, + .scpu_int_en_offset = ISOM_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask = rtd1625_isom_isr_to_scpu_int_en_mask, + .subset_mask = rtd1625_intc_isom_cfgs, + .subset_num = ARRAY_SIZE(rtd1625_intc_isom_cfgs), + }, +}; + +static const struct realtek_intc_desc rtd1625_intc_isom_desc = { + .banks = rtd1625_intc_isom_info, + .bank_num = ARRAY_SIZE(rtd1625_intc_isom_info), + .shared_irq_mask = BIT(0), +}; + +static const struct realtek_intc_mask rtd1625_intc_misc_cfgs[] = { + { MISC_NORMAL_MASK, }, +}; + +static const struct realtek_intc_mask rtd1625_intc_misc2_cfgs[] = { + { MISC2_NORMAL_MASK, }, + { MISC2_UART1_MASK, }, /* ur1 */ + { MISC2_UART2_MASK, }, /* ur2 */ +}; + +static const struct realtek_intc_info rtd1625_intc_misc_info[] = { + { + .isr_offset = MISC_ISR_OFFSET, + .scpu_int_en_offset = MISC_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask = rtd1625_misc_isr_to_scpu_int_en_mask, + .subset_mask = rtd1625_intc_misc_cfgs, + .subset_num = ARRAY_SIZE(rtd1625_intc_misc_cfgs), + }, + { + .isr_offset = MISC2_ISR_OFFSET, + .scpu_int_en_offset = MISC2_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask = rtd1625_misc_isr2_to_scpu_int_en_mask, + .subset_mask = rtd1625_intc_misc2_cfgs, + .subset_num = ARRAY_SIZE(rtd1625_intc_misc2_cfgs), + }, +}; + +static const struct realtek_intc_desc rtd1625_intc_misc_desc = { + .banks = rtd1625_intc_misc_info, + .bank_num = ARRAY_SIZE(rtd1625_intc_misc_info), + .shared_irq_mask = 0, +}; + +static const struct of_device_id realtek_intc_rtd1625_dt_matches[] = { + { + .compatible = "realtek,rtd1625-intc-iso", + .data = &rtd1625_intc_iso_desc, + }, { + .compatible = "realtek,rtd1625-intc-isom", + .data = &rtd1625_intc_isom_desc, + }, { + .compatible = "realtek,rtd1625-intc-misc", + .data = &rtd1625_intc_misc_desc, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, realtek_intc_rtd1625_dt_matches); + +static int rtd1625_intc_probe(struct platform_device *pdev) +{ + const struct realtek_intc_desc *desc; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + return realtek_intc_probe(pdev, desc); +} + +static DEFINE_NOIRQ_DEV_PM_OPS(realtek_intc_rtd1625_pm_ops, realtek_intc_suspend, + realtek_intc_resume); + +static struct platform_driver realtek_intc_rtd1625_driver = { + .probe = rtd1625_intc_probe, + .remove = realtek_intc_remove, + .driver = { + .name = "realtek_intc_rtd1625", + .of_match_table = realtek_intc_rtd1625_dt_matches, + .pm = pm_sleep_ptr(&realtek_intc_rtd1625_pm_ops), + }, +}; +module_platform_driver(realtek_intc_rtd1625_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek RTD1625 Interrupt Controller Driver"); -- 2.43.0