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Sun, 18 Oct 2026 20:01:40 -0700 (PDT) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f3c61c440sm216840185a.10.2026.10.18.20.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2026 20:01:40 -0700 (PDT) From: Alex Elder To: maxime.chevallier@bootlin.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Daniel Thompson , mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, hkallweit1@gmail.com, linux@armlinux.org.uk, richardcochran@gmail.com, p.zabel@pengutronix.de, peppe.cavallaro@st.com, joabreu@synopsys.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/5] net: stmmac: dwxgmac2: export symbols for XGMAC 3.01a DMA Date: Sun, 18 Oct 2026 22:01:27 -0500 Message-ID: <20261019030129.1470307-5-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261019030129.1470307-1-elder@riscstar.com> References: <20261019030129.1470307-1-elder@riscstar.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261018_200141_947910_377A6BEF X-CRM114-Status: GOOD ( 18.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Daniel Thompson Toshiba TC9564 is an Ethernet-AVB/TSN bridge and is essentially a small and highly-specialised SoC. Ethernet on this chip is provided by a DesignWare XGMAC. One consequence of the SoC-like design is that the internal AXI bus (used by the XGMAC for DMA) maps the PCI DMA space with a non-zero base address. This requires a translation step (happily just simple addition) to convert the PCI DMA address to the hardware DMA address. This is pretty funky so rather than push that translation logic into the core driver we intend to keep that logic inside the TC9564 platform code. In order to do that we need to export a few symbols to allow us to override some of the DMA and descriptor op tables. FWIW this approach to overriding the ops tables is similar to the mechanism currently found in dwmac-loongson.c (with the exception that we have also exported a couple of functions so we don't have to replicate their content in the TC9564 platform code). Signed-off-by: Daniel Thompson Co-developed-by: Alex Elder Signed-off-by: Alex Elder --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 7 +++++++ .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 1 + .../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 1 + .../net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 18 ++++++++++-------- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 0fe86e9942334..1b32d14c37440 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -470,4 +470,11 @@ extern const struct stmmac_dma_ops dwxgmac210_dma_ops; extern const struct stmmac_dma_ops dwxgmac301_dma_ops; extern const struct stmmac_desc_ops dwxgmac210_desc_ops; +void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan); +void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan); + #endif /* __STMMAC_DWXGMAC2_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 1a88cbaed70ca..0effdd6969d65 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1542,6 +1542,7 @@ int dwxgmac2_setup(struct stmmac_priv *priv) return 0; } +EXPORT_SYMBOL_GPL(dwxgmac2_setup); int dwxlgmac2_setup(struct stmmac_priv *priv) { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c index 6719ac6e395bc..f0e7b8ee48ac7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c @@ -374,3 +374,4 @@ const struct stmmac_desc_ops dwxgmac210_desc_ops = { .set_vlan = dwxgmac2_set_vlan, .set_tbs = dwxgmac2_set_tbs, }; +EXPORT_SYMBOL_GPL(dwxgmac210_desc_ops); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index f9a77d641eb65..2f9334d7cb922 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -63,10 +63,10 @@ static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); } -static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, - void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t phy, u32 chan) +void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t phy, u32 chan) { u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; u32 value; @@ -78,11 +78,11 @@ static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); } +EXPORT_SYMBOL_GPL(dwxgmac2_dma_init_rx_chan); -static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, - void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t phy, u32 chan) +void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan) { u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; u32 value; @@ -94,6 +94,7 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); } +EXPORT_SYMBOL_GPL(dwxgmac2_dma_init_tx_chan); static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) { @@ -673,3 +674,4 @@ const struct stmmac_dma_ops dwxgmac301_dma_ops = { .enable_sph = dwxgmac2_enable_sph, .enable_tbs = dwxgmac2_enable_tbs, }; +EXPORT_SYMBOL_GPL(dwxgmac301_dma_ops); -- 2.53.0