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Mon, 19 Oct 2026 09:43:12 -0700 Received: from build-bwicaksono-noble-20260804.internal (10.127.8.11) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 19 Oct 2026 09:43:12 -0700 From: Besar Wicaksono To: , , CC: , , , , , , , , , , , , , , , , , , , , , "Besar Wicaksono" Subject: [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics Date: Mon, 19 Oct 2026 16:42:35 +0000 Message-ID: <20261019164241.403644-1-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.43.0 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH2PEPF00048913:EE_|IA1PR12MB7710:EE_ X-MS-Office365-Filtering-Correlation-Id: cdd2b916-21e0-42ba-c4e4-08df2e001d5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|1800799024|36860700016|82310400026|56012099006|11063799006|261009223027099003|10067099003|18002099003|6133799003; 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X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_ZEN_BLOCKED_OPENDNS,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add event aliases and derived metrics for the NVIDIA Tegra410 uncore PMUs. The series covers the UCF, PCIe, PCIe target, CPU memory latency, and chip-to-chip interconnect PMUs. It provides symbolic names for the raw event encodings and metrics for bandwidth, frequency, and average read latency. Patch 1 fixes a jevents ordering problem found with this layout: the uncore events live in arch/arm64/nvidia/t410/sys/, next to the T410 core events, and without the fix jevents puts the core tlb.json (which sorts after "sys") into the sys table, so its events are lost from perf list and perf stat. Besar Wicaksono (6): perf jevents: Process model files before sys subdirectories perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU aliasing perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing .../arm64/nvidia/t410/sys/uncore-cpu_mem.json | 48 ++ .../arm64/nvidia/t410/sys/uncore-nvclink.json | 75 ++ .../arm64/nvidia/t410/sys/uncore-nvdlink.json | 48 ++ .../nvidia/t410/sys/uncore-nvlink_c2c.json | 129 ++++ .../arm64/nvidia/t410/sys/uncore-pcie.json | 247 +++++++ .../nvidia/t410/sys/uncore-pcie_tgt.json | 93 +++ .../arm64/nvidia/t410/sys/uncore-ucf.json | 693 ++++++++++++++++++ tools/perf/pmu-events/jevents.py | 4 +- 8 files changed, 1336 insertions(+), 1 deletion(-) create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvclink.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvdlink.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-nvlink_c2c.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-ucf.json -- 2.43.0