From: Besar Wicaksono <bwicaksono@nvidia.com>
To: <acme@kernel.org>, <namhyung@kernel.org>, <irogers@google.com>
Cc: <linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <vsethi@nvidia.com>,
<rwiley@nvidia.com>, <skelley@nvidia.com>, <mochs@nvidia.com>,
<rajjoshi@nvidia.com>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <john.garry@linux.dev>, <will@kernel.org>,
<james.clark@linaro.org>, <mike.leach@arm.com>,
<leo.yan@linux.dev>, <mark.rutland@arm.com>,
<alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>,
<adrian.hunter@intel.com>, <ctshao@google.com>,
"Besar Wicaksono" <bwicaksono@nvidia.com>
Subject: [PATCH 4/6] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
Date: Mon, 19 Oct 2026 16:42:39 +0000 [thread overview]
Message-ID: <20261019164241.403644-5-bwicaksono@nvidia.com> (raw)
In-Reply-To: <20261019164241.403644-1-bwicaksono@nvidia.com>
Add alias support for NVIDIA Tegra410 PCIE-TGT PMU events and metrics.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../nvidia/t410/sys/uncore-pcie_tgt.json | 93 +++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
new file mode 100644
index 000000000000..74786fc3d578
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-pcie_tgt.json
@@ -0,0 +1,93 @@
+[
+ {
+ "EventCode": "0x4",
+ "EventName": "PCIE_TGT_CYCLES",
+ "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "PCIE_TGT_RD_REQ",
+ "BriefDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x3",
+ "EventName": "PCIE_TGT_WR_REQ",
+ "BriefDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the source sends data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x0",
+ "EventName": "PCIE_TGT_RD_BYTES",
+ "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ.",
+ "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ. Destination filters work as described for PCIE_TGT_RD_REQ.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "PCIE_TGT_WR_BYTES",
+ "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ.",
+ "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ. Destination filters work as described for PCIE_TGT_WR_REQ.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_freq",
+ "MetricGroup": "PCIE_TGT_Frequency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_TGT_CYCLES / aggr_nr(PCIE_TGT_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_rd_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+ "MetricExpr": "PCIE_TGT_RD_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Average read bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_wr_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+ "MetricExpr": "PCIE_TGT_WR_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Average write bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_rd_bandwidth_to_pcie_bar",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+ "MetricExpr": "PCIE_TGT_RD_BYTES / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+ "PublicDescription": "Average read bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_wr_bandwidth_to_pcie_bar",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+ "MetricExpr": "PCIE_TGT_WR_BYTES / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+ "PublicDescription": "Average write bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+ "Compat": "1070036b",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ }
+]
--
2.43.0
next prev parent reply other threads:[~2026-10-19 17:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-19 16:42 [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
2026-10-19 16:42 ` [PATCH 1/6] perf jevents: Process model files before sys subdirectories Besar Wicaksono
2026-10-19 16:42 ` [PATCH 2/6] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing Besar Wicaksono
2026-10-19 16:42 ` [PATCH 3/6] perf jevents: Add support for NVIDIA Tegra410 PCIE " Besar Wicaksono
2026-10-19 17:50 ` Chun-Tse Shao
2026-10-19 16:42 ` Besar Wicaksono [this message]
2026-10-19 23:18 ` [PATCH 4/6] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT " Ian Rogers
2026-10-20 22:01 ` Besar Wicaksono
2026-10-20 23:12 ` Chun-Tse Shao
2026-10-19 16:42 ` [PATCH 5/6] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency " Besar Wicaksono
2026-10-19 16:42 ` [PATCH 6/6] perf jevents: Add support for NVIDIA Tegra410 C2C " Besar Wicaksono
2026-10-19 17:23 ` [PATCH 0/6] perf jevents: Add NVIDIA Tegra410 uncore PMU events and metrics James Clark
2026-10-20 19:15 ` Arnaldo Carvalho de Melo
2026-10-20 20:32 ` Ian Rogers
2026-10-20 20:38 ` Arnaldo Melo
2026-10-20 22:14 ` Besar Wicaksono
2026-10-21 1:30 ` Ian Rogers
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261019164241.403644-5-bwicaksono@nvidia.com \
--to=bwicaksono@nvidia.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=ctshao@google.com \
--cc=irogers@google.com \
--cc=james.clark@linaro.org \
--cc=john.garry@linux.dev \
--cc=jolsa@kernel.org \
--cc=jonathanh@nvidia.com \
--cc=leo.yan@linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mike.leach@arm.com \
--cc=mochs@nvidia.com \
--cc=namhyung@kernel.org \
--cc=rajjoshi@nvidia.com \
--cc=rwiley@nvidia.com \
--cc=skelley@nvidia.com \
--cc=treding@nvidia.com \
--cc=vsethi@nvidia.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox