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Signed-off-by: Besar Wicaksono --- .../arm64/nvidia/t410/sys/uncore-cpu_mem.json | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json new file mode 100644 index 000000000000..85ebe6fa20e2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/sys/uncore-cpu_mem.json @@ -0,0 +1,48 @@ +[ + { + "EventCode": "0x0", + "EventName": "CMEM_CYCLES", + "BriefDescription": "Counts elapsed MSN bridge cycles for the CMEM read-latency counters.", + "PublicDescription": "Counts elapsed Memory Switch Node (MSN) bridge cycles for the CMEM read-latency counters. All MSN instances share this clock, so the count is read from the first instance.", + "Compat": "NVDA2021", + "Unit": "nvidia_cmem_latency_pmu_" + }, + { + "EventCode": "0x1", + "EventName": "CMEM_RD_REQ", + "BriefDescription": "Counts local CMEM read requests at the edge of the UCF (post SLC), in 32-byte units, from all requesters.", + "PublicDescription": "Counts read requests at the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM), at 32-byte granularity. A read of up to 32 bytes adds one; a 64-byte read adds two. It counts reads from all requesters, local and remote, summed over all Memory Switch Node (MSN) instances and channels. There is no requester or security-state filtering.", + "Compat": "NVDA2021", + "Unit": "nvidia_cmem_latency_pmu_" + }, + { + "EventCode": "0x2", + "EventName": "CMEM_RD_CUM_OUTS", + "BriefDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each MSN bridge cycle.", + "PublicDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each Memory Switch Node (MSN) bridge cycle. Pair the two for the average read latency.", + "Compat": "NVDA2021", + "Unit": "nvidia_cmem_latency_pmu_" + }, + { + "MetricName": "cmem_freq", + "MetricGroup": "CMEM_Frequency;CMEM_Read_Latency", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CMEM_CYCLES / aggr_nr(CMEM_CYCLES)) / 1e9 / duration_time", + "ScaleUnit": "1GHz", + "BriefDescription": "MSN bridge clock frequency of the CMEM read-latency counters.", + "PublicDescription": "Average Memory Switch Node (MSN) bridge clock frequency over the measurement interval. This is the clock of the CMEM read-latency counters.", + "Compat": "NVDA2021", + "Unit": "nvidia_cmem_latency_pmu_" + }, + { + "MetricName": "cmem_avg_rd_latency", + "MetricGroup": "CMEM_Read_Latency", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CMEM_RD_CUM_OUTS / CMEM_RD_REQ) / cmem_freq", + "ScaleUnit": "1ns/request", + "BriefDescription": "Average local CMEM read latency from the edge of the UCF (post SLC) to CPU DRAM, for all requesters.", + "PublicDescription": "Average latency of the read requests counted by CMEM_RD_REQ, from the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM).", + "Compat": "NVDA2021", + "Unit": "nvidia_cmem_latency_pmu_" + } +] -- 2.43.0