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Tue, 20 Oct 2026 06:38:24 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20261020063821epsmtip1db5f8f90c6c6fff0654bb0adcd8b75c8~gKYTBB-iP0080600806epsmtip1c; Tue, 20 Oct 2026 06:38:21 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, peter.griffin@linaro.org, alim.akhtar@samsung.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, conor+dt@kernel.org, raghav.s@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, is.gandhi@samsung.com, ts.amit@samsung.com, pokala.reddy@samsung.com Subject: [PATCH v3 09/14] clk: samsung: exynos8855: add block hsi clock support Date: Tue, 20 Oct 2026 12:25:53 +0530 Message-Id: <20261020065558.1829402-10-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261020065558.1829402-1-raghav.s@samsung.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261020063824epcas5p103daef8330f45742ebeb7ab6df576e3c X-Msg-Generator: CA Content-Type: text/plain; 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CMU_HSI, this provides clocks for HSI Co-developed-by: Alim Akhtar Signed-off-by: Alim Akhtar Signed-off-by: Raghav Sharma --- drivers/clk/samsung/clk-exynos8855.c | 74 ++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c index 12b5ae54b560..0be1cefadb51 100644 --- a/drivers/clk/samsung/clk-exynos8855.c +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -19,7 +19,9 @@ #define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1) #define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) #define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1) +#define CLKS_NR_HSI (CLK_GOUT_UFS_EMBD_UNIPRO_HSI + 1) +#define EXYNOS8855_HSI_GATE_DBG_OFFSET 0x2000 #define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 #define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 @@ -1186,6 +1188,75 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, }; +/* ---- CMU_HSI --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI (0x17000000) */ +#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER 0x600 +#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER 0x610 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK 0x2000 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK 0x2038 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x203c +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2058 +#define CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long hsi_clk_regs[] __initconst = { + CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER, + CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_HSI */ +PNAME(mout_clkcmu_hsi_noc_user_p) = { "oscclk", "dout_clkcmu_hsi_noc" }; +PNAME(mout_clkcmu_hsi_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi_ufs_embd" }; + +static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI_NOC_USER, "mout_clkcmu_hsi_noc_user", + mout_clkcmu_hsi_noc_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER, 4, 1), + MUX(CLK_MOUT_HSI_UFS_EMBD_USER, "mout_clkcmu_hsi_ufs_embd_user", + mout_clkcmu_hsi_ufs_embd_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, 4, 1), +}; + +static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_HSI, "gout_cmu_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_HSI, "gout_sysreg_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_UFS_EMBD_ACLK_HSI, "gout_ufs_embd_aclk_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_UFS_EMBD_UNIPRO_HSI, "gout_ufs_embd_unipro_hsi", + "mout_clkcmu_hsi_ufs_embd_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + 21, 0, 0), +}; + +static const struct samsung_cmu_info hsi_cmu_info __initconst = { + .mux_clks = hsi_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), + .gate_clks = hsi_gate_clks, + .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), + .nr_clk_ids = CLKS_NR_HSI, + .clk_regs = hsi_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), + .sysreg_clk_regs = dcrg_memclk_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_HSI_GATE_DBG_OFFSET, + .option_offset = CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, + .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, +}; + static int __init exynos8855_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1199,6 +1270,9 @@ static int __init exynos8855_cmu_probe(struct platform_device *pdev) static const struct of_device_id exynos8855_cmu_of_match[] = { { + .compatible = "samsung,exynos8855-cmu-hsi", + .data = &hsi_cmu_info, + }, { .compatible = "samsung,exynos8855-cmu-peric", .data = &peric_cmu_info, }, { -- 2.34.1