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Wed, 21 Oct 2026 02:46:01 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e258427cesm4320300f8f.52.2026.10.21.02.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 02:46:00 -0700 (PDT) From: Luca Leonardo Scorcia To: akkun11.open@gmail.com Cc: angelogioacchino.delregno@collabora.com, bhelgaas@google.com, bmasney+clk@redhat.com, dakr@kernel.org, jbrunet+clk@baylibre.com, laura.nao@collabora.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, nicolas.frattaroli@collabora.com, o-takashi@sakamocchi.jp, sboyd@kernel.org, sjoerd@collabora.com, u.kleine-koenig@baylibre.com, wenst@chromium.org, Luca Leonardo Scorcia Subject: [PATCH 3/6] clk: mediatek: Reserve missing MT8167 clock ID Date: Wed, 21 Oct 2026 11:45:20 +0200 Message-ID: <20261021094542.59417-1-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260921102522.1640072-4-akkun11.open@gmail.com> References: <20260921102522.1640072-4-akkun11.open@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261021_104605_380187_156E8A0C X-CRM114-Status: GOOD ( 10.33 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 I tested this patch on the Sony PlayStation Classic Mini (MT8167) and unfortunately it breaks HDMI output. MediaTek HDMI PHY driver registers the hdmtx_clkdig_cts clock at runtime [1]. When this patch is applied, the following boot error appears: 10018300.hdmi-phy: error -EEXIST: failed to register clk 'hdmtx_dig_cts' (0xffff0000018539a0) 10018300.hdmi-phy: error -EEXIST: Failed to register PLL 10018300.hdmi-phy: probe with driver mediatek-hdmi-phy failed with error -17 The original problem is caused by having the HDMI PHY node disabled in the DTS, which is usually the dtsi default, but it does not happen if the HDMI PHY is enabled. If this is merged I think this error would show up on all the affected SoCs. [1] https://github.com/torvalds/linux/blob/a804c5742bff224d4cb4d25dd383554d598be32b/drivers/phy/mediatek/phy-mtk-hdmi.c#L140 -- Luca