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Thu, 22 Oct 2026 01:45:22 +0000 From: "Peng Fan (OSS)" Subject: [PATCH 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards Date: Thu, 22 Oct 2026 09:50:00 +0800 Message-Id: <20261022-8qm-v1-0-2a597cb3debd@nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAMlr2WoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzNDAyMjXYvCXF0Lc9MUgySTJONU8xQloMqCotS0zAqwKdGxEH5xaVJWanI JSKtSbS0ATFjAAWcAAAA= X-Change-ID: 20261022-8qm-875d0b4b3e7d To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Peng Fan X-Mailer: b4 0.16-dev-7bc12 X-ClientProxiedBy: MA5P287CA0133.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:1d2::7) To AM8PR04MB7874.eurprd04.prod.outlook.com (2603:10a6:20b:24d::9) X-Archived-By: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM8PR04MB7874:EE_|MI7PR04MB114164:EE_ X-MS-Office365-Filtering-Correlation-Id: 52b5de21-c199-44b7-0a2a-08df2fde22d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|19092799006|1800799024|376014|23010399003|7416014|10067099003|18002099003|261021123027099003|11063799006|261009223027099003|56012099006; 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X-Spam-Score: 0.0 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The ERR050104 cache coherency workaround for the NXP i.MX8QuadMax and i.MX8QuadPlus SoCs has been merged upstream as commit d44e08dab27d ("arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency issue"). The workaround addresses a hardware defect where the upper address bits of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were incorrectly connected, causing TLBI and IC maintenance operations exchanged between the A53 and A72 clusters to be corrupted. Before the software workaround was available, affected board DTS files worked around this issue at the DT level by removing the Cortex-A72 CPU nodes (cpu@100, cpu@101), the cpu-map topology, and associated thermal zones, effectively running the SoC as a single A53-only cluster. With the kernel-side fix in place, these DT-level workarounds could be dropped. Signed-off-by: Peng Fan --- Peng Fan (2): arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 ---------- arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi | 7 ------- 2 files changed, 17 deletions(-) --- base-commit: 4403278e4ea2f654f8130a5c03eb8b4516a0f201 change-id: 20261022-8qm-875d0b4b3e7d Best regards, -- Peng Fan