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Wed, 21 Oct 2026 23:46:42 -0700 (PDT) Received: from localhost.localdomain (dynamic-2a02-3100-ad43-d501-2c28-bb72-120d-420e.310.pool.telefonica.de. [2a02:3100:ad43:d501:2c28:bb72:120d:420e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828cd1sm10215624f8f.22.2026.10.21.23.46.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 21 Oct 2026 23:46:42 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/3] KVM: arm64: vgic-v2: Don't drop pending writes to active level IRQs Date: Thu, 22 Oct 2026 08:46:26 +0200 Message-Id: <20261022064628.4206-2-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261022064628.4206-1-kmehltretter@gmail.com> References: <20261022064628.4206-1-kmehltretter@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261022_074644_769619_234FD2CF X-CRM114-Status: GOOD ( 22.37 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 A write to GICD_ISPENDR for an active level interrupt makes the interrupt Active and Pending. It must be delivered again after it is deactivated. KVM loses the second pending state. vgic_v2_populate_lr() leaves pending_latch set for a level interrupt, while vgic_v2_compute_lr() keeps Pending and Active out of the same LR. vgic_v2_fold_lr() clears the latch after the LR becomes empty. At that point it cannot tell the original latch from one written while the interrupt was active, and clears both. Clear the original latch when the LR first reports no pending state. Keep a latch which was not represented in the LR, either because the interrupt was already active or because the guest wrote ISPENDR while the interrupt was in an LR. Clear the marker together with the latch on an ICPENDR write. A remote ISPENDR write can race with the guest ack. KVM cannot tell which happened first without synchronizing the target vCPU. Preserve the write, which may cause one extra delivery if it preceded the ack but avoids losing a write that followed it. Fixes: 67b5b673ad4d ("KVM: arm/arm64: vgic: Disallow Active+Pending for level interrupts") Assisted-by: LLM --- arch/arm64/kvm/vgic/vgic-mmio.c | 9 +++++++++ arch/arm64/kvm/vgic/vgic-v2.c | 13 ++++++++++--- include/kvm/arm_vgic.h | 1 + 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c index fddb9da0403d5..1728c78f99cfd 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.c +++ b/arch/arm64/kvm/vgic/vgic-mmio.c @@ -341,6 +341,13 @@ static void __set_pending(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len, continue; } + /* + * The guest may already have acked what is in the LR, + * in which case this is a new pending state. + */ + if (irq->on_lr) + irq->latch_written = true; + irq->pending_latch = true; if (irq->hw && !is_user) vgic_irq_set_phys_active(irq, true); @@ -427,6 +434,8 @@ static void __clear_pending(struct kvm_vcpu *vcpu, continue; } + irq->latch_written = false; + if (irq->hw && !is_user) vgic_hw_irq_cpending(vcpu, irq); else diff --git a/arch/arm64/kvm/vgic/vgic-v2.c b/arch/arm64/kvm/vgic/vgic-v2.c index 7182f63fc9382..37474ea2431c5 100644 --- a/arch/arm64/kvm/vgic/vgic-v2.c +++ b/arch/arm64/kvm/vgic/vgic-v2.c @@ -57,7 +57,7 @@ static void vgic_v2_fold_lr(struct kvm_vcpu *vcpu, u32 val) { u32 cpuid, intid = val & GICH_LR_VIRTUALID; struct vgic_irq *irq; - bool deactivated; + bool deactivated, was_active; /* Extract the source vCPU id from the LR */ cpuid = FIELD_GET(GICH_LR_PHYSID_CPUID, val) & 7; @@ -71,7 +71,8 @@ static void vgic_v2_fold_lr(struct kvm_vcpu *vcpu, u32 val) scoped_guard(raw_spinlock, &irq->irq_lock) { /* Always preserve the active bit, note deactivation */ - deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT); + was_active = irq->active; + deactivated = was_active && !(val & GICH_LR_ACTIVE_BIT); irq->active = !!(val & GICH_LR_ACTIVE_BIT); if (irq->active && vgic_irq_is_sgi(intid)) @@ -88,9 +89,15 @@ static void vgic_v2_fold_lr(struct kvm_vcpu *vcpu, u32 val) /* * Clear soft pending state when level irqs have been acked. + * A latch written while the irq was active is a new pending + * state. A write while the irq was in the LR may also have + * followed the ack, so preserve it too. */ - if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE)) + if (irq->config == VGIC_CONFIG_LEVEL && + !(val & GICH_LR_PENDING_BIT) && + !was_active && !irq->latch_written) irq->pending_latch = false; + irq->latch_written = false; /* Handle resampling for mapped interrupts if required */ vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT); diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 7be81b936bf10..28ed27d982dfc 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -292,6 +292,7 @@ struct vgic_irq { bool active:1; bool hw:1; /* Tied to HW IRQ */ bool on_lr:1; /* Present in a CPU LR */ + bool latch_written:1; /* Level only: latch set while on_lr */ refcount_t refcount; /* Used for LPIs */ u32 hwintid; /* HW INTID number */ unsigned int host_irq; /* linux irq corresponding to hwintid */ -- 2.39.5 (Apple Git-154)