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[2a02:3100:ad43:d501:2c28:bb72:120d:420e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828cd1sm10215624f8f.22.2026.10.21.23.46.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 21 Oct 2026 23:46:45 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/3] KVM: selftests: arm64: Test pending writes to active level IRQs Date: Thu, 22 Oct 2026 08:46:28 +0200 Message-Id: <20261022064628.4206-4-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261022064628.4206-1-kmehltretter@gmail.com> References: <20261022064628.4206-1-kmehltretter@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261021_234648_439845_E2AABA7E X-CRM114-Status: GOOD ( 19.23 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add a two-vCPU GICv3 test for a level SPI set pending through GICD_ISPENDR. Re-pend the interrupt while it is active, first from the handling vCPU and then from the other vCPU. Require a second delivery after deactivation in both cases. Also check that the other vCPU observes the initial pending state before the interrupt is acknowledged. Without the VGIC fix, the pending state is cleared on deactivation and the test fails before the second delivery. Assisted-by: LLM --- tools/testing/selftests/kvm/arm64/vgic_irq.c | 101 +++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/vgic_irq.c b/tools/testing/selftests/kvm/arm64/vgic_irq.c index 3cb85932ee85c..81f38e523d3c0 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_irq.c +++ b/tools/testing/selftests/kvm/arm64/vgic_irq.c @@ -959,6 +959,106 @@ static void guest_code_timer_spi(struct test_args *args, int cpuid) GUEST_DONE(); } +#define REPEND_READ 1 +#define REPEND_READ_DONE 2 +#define REPEND_WRITE 3 + +/* + * A level-sensitive SPI that is set pending through GICD_ISPENDR stays + * pending for every vCPU until it is acked. If it is set pending again while + * it is active, it becomes active and pending and must be taken a second time + * once it has been deactivated. The second pending state comes from the vCPU + * that handles the interrupt in the first round, and from the other vCPU in + * the second. + */ +static void guest_code_level_repend(struct test_args *args, int cpuid) +{ + int i; + + gic_init(GIC_V3, 2); + + gic_set_eoi_split(1); + gic_set_priority_mask(CPU_PRIO_MASK); + + if (cpuid == 0) { + u32 intid; + + local_irq_disable(); + + gic_irq_set_config(MIN_SPI, false); + gic_set_priority(MIN_SPI, IRQ_DEFAULT_PRIO); + gic_irq_enable(MIN_SPI); + + for (i = 0; i < 2; i++) { + gic_irq_set_pending(MIN_SPI); + + if (i == 1) { + /* Not acked yet: the other vCPU sees it pending */ + WRITE_ONCE(args->shared_data, REPEND_READ); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_READ_DONE); + } + + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + intid = wait_for_and_activate_irq(); + GUEST_ASSERT_EQ(intid, MIN_SPI); + + if (i == 0) { + gic_irq_set_pending(MIN_SPI); + } else { + WRITE_ONCE(args->shared_data, REPEND_WRITE); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) == REPEND_WRITE); + } + + GUEST_ASSERT(gic_irq_get_active(MIN_SPI)); + gic_set_eoi(intid); + gic_set_dir(intid); + isb(); + + /* The second pending state must not have been lost */ + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + intid = wait_for_and_activate_irq(); + GUEST_ASSERT_EQ(intid, MIN_SPI); + + gic_set_eoi(intid); + gic_set_dir(intid); + isb(); + + GUEST_ASSERT(!gic_irq_get_active(MIN_SPI)); + GUEST_ASSERT(!gic_irq_get_pending(MIN_SPI)); + GUEST_ASSERT_EQ(gic_get_and_ack_irq(), IAR_SPURIOUS); + } + } else { + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_READ); + + for (i = 0; i < 64; i++) + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + + WRITE_ONCE(args->shared_data, REPEND_READ_DONE); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_WRITE); + + gic_irq_set_pending(MIN_SPI); + + WRITE_ONCE(args->shared_data, 0); + dsb(ishst); + } + + GUEST_DONE(); +} + static void *test_vcpu_run(void *arg) { struct kvm_vcpu *vcpu = arg; @@ -1073,6 +1173,7 @@ int main(int argc, char **argv) test_vgic_two_cpus(guest_code_asym_dir); test_vgic_two_cpus(guest_code_group_en); test_vgic_two_cpus(guest_code_timer_spi); + test_vgic_two_cpus(guest_code_level_repend); } else { test_vgic(nr_irqs, level_sensitive, eoi_split); } -- 2.39.5 (Apple Git-154)