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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-55be9880a99sm909562b6e.14.2026.10.23.00.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 00:34:00 -0700 (PDT) From: James Hilliard Date: Fri, 23 Oct 2026 01:33:50 -0600 Subject: [PATCH 2/3] serial: 8250_dw: configure the Allwinner H616 UART X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261023-submit-h616-uart-fifo-v1-v1-2-e4a3bae2eba8@gmail.com> References: <20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com> In-Reply-To: <20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_003402_058342_AFE88A70 X-CRM114-Status: GOOD ( 21.96 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 H616 has 256-byte transmit and receive FIFOs, but its optional DesignWare component parameter register reads as zero. Generic 16550 probing leaves the port using the 16-byte FIFO configuration and its trigger-level table. DMA attachment also depends on a FIFO size being available during probe, so these ports do not reach the existing 8250 DMA path. Use a fixed port configuration for the H616 compatible, with a 256-byte transmit load and the documented receive thresholds of 1, 64, 128 and 254 bytes. Select the quarter-full receive trigger by default. Skip optional-register probing for this fixed configuration. H616 has debug-divisor and RS485 control registers at the offsets used to detect DesignWare hardware RS485 and fractional-divisor support. Probing these offsets writes unrelated registers and can select incompatible callbacks. Keep the BUSY-safe integer divisor hook and software RS485 handling. Use the existing SKIP_SET_RATE quirk to keep the UART clock enabled during termios changes. Its clock is a gate on the shared APB2 source, rather than an independent baud-rate generator. Attach DMA from the fixed configuration before registering the port. The 8250 core installs its FIFO defaults during registration, after the probe's FIFO-size test. Configure single-byte RX and TX bursts because the peripheral request can correspond to just one character. The existing startup path requests the firmware-described channels and falls back to PIO when they are unavailable or the port is a kernel console. Signed-off-by: James Hilliard --- drivers/tty/serial/8250/8250.h | 1 + drivers/tty/serial/8250/8250_dw.c | 45 +++++++++++++++++++++++++++++++------ drivers/tty/serial/8250/8250_port.c | 8 +++++++ 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 21ed9c41b751..0f8c1b0b4a71 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -77,6 +77,7 @@ enum uart_port_type { /* Internal 8250 only */ UART_PORT_AIROHA = 124, UART_PORT_AIROHA_HS = 125, + UART_PORT_DW_APB_256 = 126, }; #define UART_CAP_FIFO BIT(8) /* UART has FIFO */ diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index eca02e8bd6d1..f03051740be0 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -63,6 +63,9 @@ struct dw8250_platform_data { u8 usr_reg; u32 cpr_value; + /* Use a fixed configuration instead of probing optional registers. */ + unsigned int type; + unsigned int dma_maxburst; unsigned int quirks; }; @@ -630,6 +633,18 @@ static void dw8250_shutdown(struct uart_port *port) d->no_int_count = 0; } +static void dw8250_setup_port_fixed(struct uart_8250_port *up, unsigned int type) +{ + struct uart_port *p = &up->port; + + p->type = type; + p->flags |= UPF_FIXED_TYPE; + p->rs485_config = serial8250_em485_config; + p->rs485_supported = serial8250_em485_supported; + up->rs485_start_tx = serial8250_em485_start_tx; + up->rs485_stop_tx = serial8250_em485_stop_tx; +} + static int dw8250_probe(struct platform_device *pdev) { struct uart_8250_port uart = {}, *up = &uart; @@ -765,14 +780,21 @@ static int dw8250_probe(struct platform_device *pdev) dw8250_setup_dma_filter(p, data); - if (!data->skip_autocfg) - dw8250_setup_port(p); - - /* If we have a valid fifosize, try hooking up DMA */ - if (p->fifosize) { - data->data.dma.rxconf.src_maxburst = p->fifosize / 4; - data->data.dma.txconf.dst_maxburst = p->fifosize / 4; + if (data->pdata && data->pdata->type) { + dw8250_setup_port_fixed(up, data->pdata->type); + data->data.dma.rxconf.src_maxburst = data->pdata->dma_maxburst; + data->data.dma.txconf.dst_maxburst = data->pdata->dma_maxburst; up->dma = &data->data.dma; + } else { + if (!data->skip_autocfg) + dw8250_setup_port(p); + + /* If we have a valid fifosize, try hooking up DMA */ + if (p->fifosize) { + data->data.dma.rxconf.src_maxburst = p->fifosize / 4; + data->data.dma.txconf.dst_maxburst = p->fifosize / 4; + up->dma = &data->data.dma; + } } data->data.uport = serial8250_register_8250_port(up); @@ -854,6 +876,14 @@ static const struct dw8250_platform_data dw8250_dw_apb = { .usr_reg = DW_UART_USR, }; +static const struct dw8250_platform_data dw8250_h616_data = { + .usr_reg = DW_UART_USR, + .type = UART_PORT_DW_APB_256, + /* A peripheral request can correspond to just one character. */ + .dma_maxburst = 1, + .quirks = DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct dw8250_platform_data dw8250_octeon_3860_data = { .usr_reg = OCTEON_UART_USR, .quirks = DW_UART_QUIRK_OCTEON, @@ -904,6 +934,7 @@ static const struct dw8250_platform_data dw8250_tda54 = { static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "allwinner,sun50i-h616-uart", .data = &dw8250_h616_data }, { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index db066a42f61d..e99d35880a68 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -335,6 +335,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 4}, .flags = UART_CAP_FIFO, }, + [UART_PORT_DW_APB_256] = { + .name = "DW APB UART 256", + .fifo_size = 256, + .tx_loadsz = 256, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, + .rxtrig_bytes = {1, 64, 128, 254}, + .flags = UART_CAP_FIFO | UART_CAP_NOTEMT, + }, }; /* Uart divisor latch read */ -- 2.53.0