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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6gNdFaoUvervg9j7DTGiRceZpDj1MHSA9P0OuCsgA/l6bpPc46AwA675AQO5g1nrOyzEtg13ScHCwMpCfFhoP534LcmqO3kZI5MAWRXT3Of33wF6lF0O2XyX/9EVuWNL3RDrNHYVlvl7L7A2+Gc1Vn5TwI9YjSfkOELuixTt+2Lefy7FL3YfEz+kIuFU5QDSNWII6NZi2An0Vu03YVlxP2ZrDz8japz15OM/z6tKrL545As9/aD15unyZ2GxO2m/xTi63R/BrV1WgBidTFf2cOLkp9+Ge8AjyuCv/+im0mSLkAnWAb9DP0xBfs/kZhbyYweU1e1ES4QWslnJ5jhazrrODJahufJGcXj4/fyZavvChumfbU2iINj292tVnftTJw/t09iOnWALRk271vRZCE5gFo7LToxnR3W4LyBJkHEFIJL2kBuMBb8vjNA77gzM X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2026 13:28:11.8782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ae9d1a7-71d7-4ab7-8a79-08df31097c41 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: ZR1PEPF0000E6B6.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7158 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_142819_689269_900177D4 X-CRM114-Status: GOOD ( 12.30 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-19.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Gwenael Treuveur Add the clock identifiers needed to allocate the D3 peripherals to the Cortex-M0 (CPU3 domain) and to enable their autonomous mode: - CK_CPU3 and CK__C3: allocation of the CPU3 domain and of the D3 peripherals to CPU3 - CK_CPU3_AM and CK__AM: autonomous mode of the CPU3 domain and of the D3 peripherals - CK_HSI_KER_ON, CK_HSE_KER_ON and CK_MSI_KER_ON: kernel clocks of the HSI, HSE and MSI oscillators Add the matching SCMI clocks: CK_SCMI_HSI_KER_ON, CK_SCMI_HSE_KER_ON, CK_SCMI_MSI_KER_ON and the autonomous mode clocks owned by the SCMI server (CK_SCMI_GPIOZ_AM, CK_SCMI_IPCC2_AM, CK_SCMI_LPDMA_AM and CK_SCMI_RTC_AM). The three kernel clocks of the HSI, HSE and MSI oscillators are also added at the end of the RCC input clocks. They are optional, so that the existing device trees remain valid. Signed-off-by: Gwenael Treuveur Signed-off-by: Gabriel Fernandez --- .../bindings/clock/st,stm32mp25-rcc.yaml | 9 +++++- include/dt-bindings/clock/st,stm32mp25-rcc.h | 35 ++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 3b7925d2c175..423016ecb602 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -32,6 +32,7 @@ properties: const: 1 clocks: + minItems: 80 items: - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz) - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz) @@ -113,6 +114,9 @@ properties: - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 - description: CK_SCMI_PLL3 PLL3 clock - description: clk_dsi_txbyte DSI byte clock + - description: CK_SCMI_HSI_KER_ON Kernel High Speed Internal oscillator + - description: CK_SCMI_HSE_KER_ON Kernel High Speed External oscillator + - description: CK_SCMI_MSI_KER_ON Kernel Low Power Internal oscillator access-controllers: maxItems: 1 @@ -214,6 +218,9 @@ examples: <&scmi_clk CK_SCMI_TIMG1>, <&scmi_clk CK_SCMI_TIMG2>, <&scmi_clk CK_SCMI_PLL3>, - <&clk_dsi_txbyte>; + <&clk_dsi_txbyte>, + <&scmi_clk CK_SCMI_HSI_KER_ON>, + <&scmi_clk CK_SCMI_HSE_KER_ON>, + <&scmi_clk CK_SCMI_MSI_KER_ON>; }; ... diff --git a/include/dt-bindings/clock/st,stm32mp25-rcc.h b/include/dt-bindings/clock/st,stm32mp25-rcc.h index cef997508b56..53c65e9a12f6 100644 --- a/include/dt-bindings/clock/st,stm32mp25-rcc.h +++ b/include/dt-bindings/clock/st,stm32mp25-rcc.h @@ -365,6 +365,34 @@ #define HSE_DIV2_CK 343 #define CK_KER_ETR 344 #define CK_KER_STM 345 +#define CK_HSI_KER_ON 346 +#define CK_HSE_KER_ON 347 +#define CK_MSI_KER_ON 348 +#define CK_CPU3 349 +#define CK_ADF1_C3 350 +#define CK_GPIOZ_C3 351 +#define CK_I2C8_C3 352 +#define CK_I3C4_C3 353 +#define CK_LPDMA_C3 354 +#define CK_LPTIM3_C3 355 +#define CK_LPTIM4_C3 356 +#define CK_LPTIM5_C3 357 +#define CK_LPUART1_C3 358 +#define CK_RTC_C3 359 +#define CK_SPI8_C3 360 +#define CK_ADF1_AM 361 +#define CK_CPU3_AM 362 +#define CK_GPIOZ_AM 363 +#define CK_I2C8_AM 364 +#define CK_I3C4_AM 365 +#define CK_IPCC2_AM 366 +#define CK_LPDMA_AM 367 +#define CK_LPTIM3_AM 368 +#define CK_LPTIM4_AM 369 +#define CK_LPTIM5_AM 370 +#define CK_LPUART1_AM 371 +#define CK_RTC_AM 372 +#define CK_SPI8_AM 373 #define CK_SCMI_ICN_HS_MCU 0 #define CK_SCMI_ICN_SDMMC 1 @@ -490,5 +518,12 @@ #define CK_SCMI_BUS_STM 122 #define CK_SCMI_KER_STM 123 #define CK_SCMI_KER_ETR 124 +#define CK_SCMI_HSI_KER_ON 125 +#define CK_SCMI_HSE_KER_ON 126 +#define CK_SCMI_MSI_KER_ON 127 +#define CK_SCMI_GPIOZ_AM 128 +#define CK_SCMI_IPCC2_AM 129 +#define CK_SCMI_LPDMA_AM 130 +#define CK_SCMI_RTC_AM 131 #endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */ -- 2.43.0