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Fri, 23 Oct 2026 09:30:19 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2C3484102B47; Fri, 23 Oct 2026 17:30:18 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com, Frank Li Subject: [PATCH v4 1/5] dmaengine: arm-dma350: Fix source trigger bit Date: Fri, 23 Oct 2026 17:30:13 +0800 Message-ID: <20261023093017.3248454-2-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261023093017.3248454-1-Jelly.Jia@cixtech.com> References: <20261023093017.3248454-1-Jelly.Jia@cixtech.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E7:EE_|SEZPR06MB6038:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 2808309e-4376-4109-4e20-08df30e8411f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|7416014|82310400026|36860700016|261022105027099003|261021123027099003|261021121427099003|261009223027099003|10067099003|56012099006|18002099003|22082099003|6133799003; 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X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 CH_CTRL_USESRCTRIGIN is the source trigger enable bit in CH_CTRL and must use bit 25, not bit 26 which is the destination trigger enable bit (CH_CTRL_USEDESTRIGIN). The constant has no users yet, but enabling the source trigger input would silently enable the destination trigger input instead, breaking any transfer that waits for a peripheral request. Fix it before the first user arrives. Fixes: 5d099706449d ("dmaengine: Add Arm DMA-350 driver") Signed-off-by: Jelly Jia Reviewed-by: Frank Li --- drivers/dma/arm-dma350.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 09403aca8bb0..4e17130de6c8 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -63,7 +63,7 @@ #define CH_CTRL 0x0c #define CH_CTRL_USEDESTRIGIN BIT(26) -#define CH_CTRL_USESRCTRIGIN BIT(26) +#define CH_CTRL_USESRCTRIGIN BIT(25) #define CH_CTRL_DONETYPE GENMASK(23, 21) #define CH_CTRL_REGRELOADTYPE GENMASK(20, 18) #define CH_CTRL_XTYPE GENMASK(11, 9) -- 2.54.0