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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: D2hxLwNs0S6N3Pl3r5+RgmKxpFtSZSnkkSy4ndu1sRdxlFwfjM2RSUh6nEq1LvD/dKd2Hh5nKNipWhC3CqrRphjIex4Qo2AodLjdx1ooXBC/KxAHUUKeqP9PmrHyaXIVV4bGMstu0/I98p7TbCUUw9Qijx6vrcHJxV+x7BQFRSkhHE4WCjD3KdaVbIyjBg0qzZeizM17wR54txEyhEu6h6yYIgPVbQ7fCph2KHOvCScKaYkGmoWGo7Ea6QZiTYHZdWZzH4MXjXkBZqqy5Jw6opPqYahGZiNJXoIWlDm5/RhAZXdaHuWeTSRDUBe0Z+u+tiMOkGj+ShCl0GmJWN0GNigoU/LEGb2GUtzXWptL7JPjjepcEltjSdUMfjfJfiKPOz2z5SNcIgUGRtxI4+1OnjDWsbHii0mIfG0Xng2ygcrnXx4fBGFd/yiDjD9towp7 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2026 09:30:20.1273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81533a57-f34d-4117-04b0-08df30e841bf X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CA.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE3PR06MB9217 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_023033_042882_E1F3F986 X-CRM114-Status: GOOD ( 12.57 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 DMA-350 integrations may gate the controller with a clock or hold it in reset. Enable an optional clock and deassert an optional reset before accessing the controller registers. Use the deasserted reset helper rather than requesting a reset pulse. This also supports reset controllers that only implement assert and deassert operations. Both resources remain optional, so existing integrations without them are unchanged. Signed-off-by: Jelly Jia --- drivers/dma/arm-dma350.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index f62ff6a9f490..9cb5b2f03113 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include @@ -1199,12 +1201,24 @@ static void d350_free_chan_resources(struct dma_chan *chan) static int d350_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct reset_control *reset; + struct clk *clk; struct d350 *dmac; void __iomem *base; u32 reg; int ret, nchan, dw, aw, r, p; bool coherent, memset; + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to enable clock\n"); + + reset = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); + if (IS_ERR(reset)) + return dev_err_probe(dev, PTR_ERR(reset), + "failed to deassert reset\n"); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); -- 2.54.0