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Fri, 23 Oct 2026 05:16:37 -0700 (PDT) Received: from localhost ([2a03:2880:32ff:4f::]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46a5cf5540sm95824066b.78.2026.10.23.05.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 05:16:37 -0700 (PDT) From: Vlad Poenaru To: Jinqian Yang , Thomas Gleixner , Marc Zyngier Cc: Lorenzo Pieralisi , Michael Chan , Pavan Chebbi , Jakub Kicinski , Breno Leitao , Andrew Preece , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, regressions@lists.linux.dev Subject: Re: [PATCH] irqchip/gic-v3-its: Enable dynamic MSI-X allocation Date: Fri, 23 Oct 2026 05:16:35 -0700 Message-ID: <20261023121635.2190639-1-vlad.wing@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261022193620.2152038-1-vlad.wing@gmail.com> References: <20261022193620.2152038-1-vlad.wing@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_051642_574154_9C1D2D35 X-CRM114-Status: GOOD ( 10.82 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Two updates on this report. First, a correction: it is not specific to our debug config. Our production config hits it as well, on every Grace + BCM57508 machine we tried, at the same point in boot. Second, the root cause is in bnxt_en, and this commit only exposes it. When the channel count is raised, bnxt_check_rings() allocates the extra MSI-X vectors before firmware has reserved them for the function. On BCM57508, writes to MSI-X table entries beyond the reserved IRQs don't stick, so the message written when the vectors are activated is lost, and the entries stay zero after the reservation. x86 never notices because GENERIC_IRQ_RESERVATION_MODE makes the PCI MSI domains MSI_FLAG_MUST_REACTIVATE and the message is written again at request_irq() time. With this commit, arm64 GICv3 takes the same dynamic path but writes the message only once, at allocation. Instrumenting the driver showed it directly. After the channel count went from 18 to 32, MSI-X entries 18-31 read back as all zero, while the cached msi_msg and the ITS LPI mapping were correct. Exactly the 14 rings on those vectors lost their completions. The fix is posted to netdev: https://lore.kernel.org/all/20261023121321.2127263-1-vlad.wing@gmail.com/ With it, the same machine runs cleanly through the channel change and the ring resize. I don't think the ITS change needs to be reverted. #regzbot monitor: https://lore.kernel.org/all/20261023121321.2127263-1-vlad.wing@gmail.com/ Thanks, Vlad