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Fri, 23 Oct 2026 19:24:56 -0700 (PDT) Received: from ASHA ([2001:630:3c1:164:1a66:daff:fe85:4026]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a5698f1sm21088415e9.8.2026.10.23.19.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 19:24:54 -0700 (PDT) From: Amir Noohi To: Thomas Gleixner , Marc Zyngier , Oliver Upton Cc: Radu Rendec , Igor Velkov , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Christoffer Dall , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Amir Noohi Subject: [PATCH 1/2] genirq/manage: Provide irq_set_percpu_irqchip_state() Date: Sat, 24 Oct 2026 02:24:49 +0000 Message-ID: <20261024022450.629980-2-amirmnoohi@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261024022450.629980-1-amirmnoohi@gmail.com> References: <20261024022450.629980-1-amirmnoohi@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261023_192458_681489_21B1508E X-CRM114-Status: GOOD ( 19.54 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 irq_set_irqchip_state() acquires the bus lock and the descriptor lock of the interrupt. A per CPU devid interrupt has a single descriptor for all CPUs, while its irqchip state is per CPU, e.g. each GICv3 redistributor holds the active and pending state of the PPIs of its own CPU and GICv5 keeps that state in per CPU system registers. Callers which modify that state have to be pinned to the CPU anyway, so the descriptor lock only serializes CPUs which update their own private state. KVM on arm64 sets the active state of the host timer interrupts on every vCPU load, i.e. on every KVM_RUN ioctl and every time a vCPU thread is scheduled in. When many CPUs load vCPUs at the same time, they all spin on the descriptor lock of the same interrupt, even when every vCPU has a physical CPU of its own. A global serialization point on the same path was removed before in commit 64b6d1d7a845 ("genirq: Get rid of global lock in irq_do_set_affinity()"). Provide irq_set_percpu_irqchip_state(), which sets the irqchip state of a per CPU devid interrupt on the calling CPU without acquiring the descriptor lock. The irqchip callback is still invoked with interrupts disabled. The caller has to have preemption disabled and has to ensure that the interrupt is neither freed nor reconfigured concurrently, which is the case for an interrupt it has requested. Interrupt chips which require a bus lock are rejected, as the bus lock may sleep and cannot be taken with preemption disabled. The function is not exported as its only user, KVM on arm64, cannot be built as a module. Signed-off-by: Amir Noohi --- include/linux/interrupt.h | 2 ++ kernel/irq/manage.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 3bf969ad8fe0..ab20129615d4 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -507,6 +507,8 @@ extern int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool *state); extern int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool state); +int irq_set_percpu_irqchip_state(unsigned int irq, enum irqchip_irq_state which, + bool state); #ifdef CONFIG_IRQ_FORCED_THREADING # ifdef CONFIG_PREEMPT_RT diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index bdb47837c66f..e76fe1cec9fb 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -2777,6 +2777,42 @@ int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool v } EXPORT_SYMBOL_GPL(irq_set_irqchip_state); +/** + * irq_set_percpu_irqchip_state - Set the irqchip state of a per CPU interrupt + * @irq: Linux interrupt number of a per CPU devid interrupt + * @which: State to be set (one of IRQCHIP_STATE_*) + * @val: Value corresponding to @which + * + * Variant of irq_set_irqchip_state() which sets the state of the calling + * CPU's instance of a per CPU devid interrupt without acquiring the + * interrupt descriptor lock. The descriptor and its lock are shared by all + * CPUs while the state is not, so acquiring the lock only serializes CPUs + * which modify their own state. + * + * Must be called with preemption disabled on an interrupt which has been + * requested, so that the interrupt chip hierarchy cannot change + * concurrently. Interrupt chips which require a bus lock are not supported. + * + * Return: 0 on success, a negative error code otherwise. + */ +int irq_set_percpu_irqchip_state(unsigned int irq, enum irqchip_irq_state which, bool val) +{ + struct irq_desc *desc = irq_to_desc(irq); + struct irq_chip *chip; + + lockdep_assert_preemption_disabled(); + + if (WARN_ON_ONCE(!desc || !irq_settings_is_per_cpu_devid(desc))) + return -EINVAL; + + chip = irq_desc_get_chip(desc); + if (WARN_ON_ONCE(chip->irq_bus_lock || chip->irq_bus_sync_unlock)) + return -EINVAL; + + guard(irqsave)(); + return __irq_set_irqchip_state(desc, which, val); +} + /** * irq_has_action - Check whether an interrupt is requested * @irq: The linux irq number -- 2.53.0