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Sat, 24 Oct 2026 14:28:53 -0700 (PDT) Received: from ASHA ([2001:630:3c1:164:1a66:daff:fe85:4026]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a2e8f25sm77497285e9.14.2026.10.24.14.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 14:28:52 -0700 (PDT) From: Amir Noohi To: Marc Zyngier Cc: Thomas Gleixner , Oliver Upton , Radu Rendec , Igor Velkov , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Christoffer Dall , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] genirq/manage: Provide irq_set_percpu_irqchip_state() Date: Sat, 24 Oct 2026 21:28:44 +0000 Message-ID: <20261024212844.3405617-1-amirmnoohi@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <87se1v8f2r.wl-maz@kernel.org> References: <20261024022450.629980-1-amirmnoohi@gmail.com> <20261024022450.629980-2-amirmnoohi@gmail.com> <87se1v8f2r.wl-maz@kernel.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261024_142855_451563_C7FFBCD1 X-CRM114-Status: GOOD ( 15.59 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Marc, On Sat, 24 Oct 2026 13:21:00 +0100, Marc Zyngier wrote: > It really feels like a leap of faith. > > There is nothing that says that it is safe to call this without > holding the global lock. For all we know, drivers have been relying on > it for a good decade, and I don't feel confident letting things rip > just because it (mostly) works with the GIC. > > At the very least, something exposed by the irqchip (a per-IRQ flag?) > should tell you whether it is safe to elide the lock. Agreed, and v2 does that. There's a new IRQCHIP_PERCPU_STATE_LOCKLESS flag, and irq_set_percpu_irqchip_state() only skips the descriptor lock if the chip implementing irq_set_irqchip_state() has it set. Otherwise, or if there's a bus lock, it just calls irq_set_irqchip_state(), so drivers that don't opt in see no change. Only GICv3 sets it, in a separate patch. For SGIs/PPIs/EPPIs its callback only touches the local redistributor (gic_data_rdist_sgi_base() and the RWP poll), nothing shared. FWIW, irq-gic.c, irq-gic-v3.c and irq-gic-v5.c are the only drivers with both per-CPU devid interrupts and an irq_set_irqchip_state() callback. KVM's own timer chip (GICv5, no HW deactivation) doesn't set it either, so those keep the lock. On GICv2 in QEMU it still takes the lock like mainline does (333k vs 321k acquisitions in lock_stat, within 4%), and on GICv3 it doesn't take it at all. arch_timer, arch_timer_edge_cases, vgic_irq and vgic_init pass on the Altra. Under QEMU with lockdep, DEBUG_PREEMPT and DEBUG_ATOMIC_SLEEP, the selftests pass on GICv3 (VHE and nVHE) and GICv2 (the vGICv3 ones skip there). No splats. I made it a chip flag since it's about the callback, but I can make it per-IRQ if you prefer. Thanks, Amir