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Mon, 26 Oct 2026 01:27:37 -0700 (PDT) Received: from osman.mioffice.cn ([43.224.245.178]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3adebfa3794sm7530156a91.14.2026.10.26.01.27.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 01:27:37 -0700 (PDT) From: Zhan Xusheng To: zhangqiao22@huawei.com Cc: tglx@linutronix.de, jstultz@google.com, sboyd@kernel.org, peterz@infradead.org, maz@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhanxusheng@xiaomi.com, Zhan Xusheng Subject: Re: [QUESTION] sched/clock: Potential timestamp jump due to inter-CPU counter skew? Date: Mon, 26 Oct 2026 16:27:30 +0800 Message-ID: <20261026082730.2117173-1-zhanxusheng1024@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261026_012738_689289_68AFD50F X-CRM114-Status: GOOD ( 12.06 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Qiao, On Mon, Oct 26, 2026 at 02:53:25PM +0800, Zhang Qiao wrote: > 1. Are there hardware or architecture specifications (e.g., ARM64 architected > timers, RISC-V) requiring counters on all CPUs—including those on different > dies/sockets—to be perfectly synchronized? If skew is permitted, is there a > specified maximum allowed skew? RISC-V's Zicntr extension requires the real-time clocks of all harts to be synchronized to within one tick. On arm64 the system counter is meant to give all PEs a common view of time, and keeping the copies on separate dies in step is the implementation's job. The kernel has no tolerance for skew. The counter errata handled in arm_arch_timer.c (Freescale A-008585, HiSilicon 161010101, Cortex-A73 858921, Allwinner A64) are all reads on a single CPU returning a wrong value, worked around by reading twice; none of them is skew between CPUs. > 2. If the sequence above is theoretically possible, does generic sched_clock() > already have a mechanism to handle a counter read that lags behind the shared > epoch_cyc? No. __sched_clock() masks the difference and converts it directly. Timekeeping's clocksource_delta() returns 0 when the masked delta exceeds max_delta, but sched_clock has no such check, so a read behind epoch_cyc gives a delta of nearly a full period and cyc * mult overflows. Thanks, Zhan Xusheng