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[2a02:3100:a45b:7d01:5035:b393:698f:53f0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ecdfd8dsm24290569f8f.56.2026.10.27.20.31.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Oct 2026 20:31:39 -0700 (PDT) From: Karl Mehltretter To: Steven Rostedt , Peter Zijlstra , Thomas Gleixner , Sebastian Andrzej Siewior Cc: Karl Mehltretter , Catalin Marinas , Will Deacon , Mark Rutland , Ingo Molnar , Andy Lutomirski , Frederic Weisbecker , "Paul E. McKenney" , Boqun Feng , Waiman Long , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Hongyan Xia , Jonathan Corbet , Shuah Khan , Randy Dunlap , Andrew Morton , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-arm-kernel@lists.infradead.org, linux-trace-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 00/13] entry: Classify very early hardirq entry and return-tail callbacks Date: Wed, 28 Oct 2026 04:31:14 +0100 Message-Id: <20261028033127.82193-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261027_203145_386071_0A636D59 X-CRM114-Status: GOOD ( 20.72 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Tracing still needs a transition recursion allowance because a callback can run after architectural hardirq entry but before generic entry updates preempt_count(). Steven asked whether HARDIRQ_OFFSET could be installed early enough for those callbacks to observe hardirq context. This RFC implements that contract for arm64. arm64 must first distinguish ordinary interrupts from pseudo-NMIs. For an ordinary interrupt, stage the raw preempt-count addition and establish lockdep state immediately after that decision and before instrumentable entry work. Keep time, tick, RCU and IRQ accounting at the existing generic boundary. With DEBUG_PREEMPT and without separate reschedule bits, an already-negative count preserves the legacy DEBUG_LOCKS_WARN_ON() oops short circuit, attempts deferred reporting at the instrumentable finish, and skips post-add bookkeeping and the matching subtraction when rejected. The exit side has a second gap. Keep any applied hardirq count and lockdep classification through traceable generic exit work, then remove them before a possible schedule. Carry ordinary-hardirq provenance through that schedule in a compact three-state byte, keeping irqentry_state_t two bytes wide, and restore a classification-only tail around architecture tracing, deferred hrtimer work, IRQ-on preparation and context-tracking preparation. The tail does not repeat RCU, tick or IRQ accounting. This is a design RFC, not a merge-ready proposal. The questions are: - Should generic entry expose separate raw-update and bookkeeping phases? - Are preempt-count and lockdep state sufficient for the return tail? - Is arm64 a suitable first user of this contract? The series is based on d135ab453a74 ("Merge tag 'backlight-next-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight"). Patches 1 and 2 include two arm64 noinstr inlining prerequisites so the series applies directly to mainline: - "arm64: Always inline raw preempt count updates" provenance: https://lore.kernel.org/all/c3a90368dd6c096af9d918e036a27728696fb8a4.1786603168.git.hongyan.xia@transsion.com/ - "arm64: percpu: Annotate __kern_my_cpu_offset() as '__always_inline'" provenance: https://lore.kernel.org/r/20260918161407.2300-12-will@kernel.org The first is the relevant hunk extracted from Hongyan Xia's larger posted RFC. The second is a current-mainline rebase of Will Deacon's posted patch. They preserve the authorship and links of the original submissions. Repository: https://github.com/kmehltretter82/linux prerequisites: steve-early-hardirq-arm64-prereqs-v2-20261027 8bdce63fa17d generic core: steve-early-hardirq-core-v2-folded-20261027 8651af55ecbc arm64 RFC: steve-early-hardirq-arm64-rfc-v2-folded-20261027 56016d197e1b The transition recursion slots remain unchanged. A separate recursion-lifetime series keeps the task recursion bit inside one preemption-disabled interval. A development-only patch removed the slots for a matched experiment. Neither that removal nor the lifetime series is part of this RFC. All three kernels in the experiment contained this early-hardirq series. On a native 16-vCPU Google Axion system, matched arm64 debug kernels completed 100 deterministic ftrace callback and IPI overlaps per cell: done litmus mixed collisions Slots kept, lifetime fix 100/100 0 0 0 Slots removed, no fix 100/100 33 60 13 Slots removed, lifetime 100/100 0 0 0 The litmus and mixed columns count ftrace recursion records. The collisions column counts transition-sensitive scheduler and return-tail records. Complete dmesg captures were clean in all three cells. The second cell is a counterexample to removing the slots without the lifetime fix in the tested path. The third supports the combined design on this machine. It does not establish every architecture-specific early-entry interval, so this RFC retains the slots and keeps the lifetime work separate. Before this rebase, the patch-identical tree was validated across a nine-cell cross-architecture W=1 full-link matrix: RISC-V 64, i386, powerpc64le, arm64, x86-64 and ARM32 with GCC 13.3 and Clang/LLD 18.1.3. It also passed 600-second arm64 SMP8 and RISC-V SMP14 stress gates, a RISC-V AIA/IMSIC SMP1/SMP2/SMP8 gate under QEMU 11.1.50, and a focused four-row DEBUG_PREEMPT staged-add oops oracle with 403 of 403 locking selftests. An ARM64 PREEMPT_RT SMP4 build passed targeted return-tail tasklet and forced-thread timer closure tests, three SMP2 priority-masked pseudo-NMI return runs, and an SMP1 NO_HZ_IDLE and RCU_EQS_DEBUG return gate with 386 Startirq-to-Endirq intervals and 1,229 IRQ-disable/enable pairs. All patches remain unchanged according to git range-diff after the rebase. Changes since v1: - rebase onto d135ab453a74 and include the two arm64 noinstr inlining prerequisites as patches 1 and 2 so the series applies directly to mainline - keep the recursion-lifetime change in a separate series - carry a scoped hardirq-entry cookie across staged count updates so !HAS_SEPARATE_PREEMPT_RESCHED_BITS && DEBUG_PREEMPT configurations preserve the legacy DEBUG_LOCKS_WARN_ON() oops decision and skip post-add work and teardown when rejected - encode ordinary-hardirq provenance and staged-count application in a three-state byte so irqentry_state_t remains two bytes wide - fully initialize the arm64 EL1 debug entry state before provenance is added - retain irqentry_exit_pcpu_adjust() ordering across the return tail - accept and test nonzero nested lockdep hardirq depth in the tail - add a matched native test of the separate recursion-lifetime work and - tighten the contract and documentation wording v1: https://lore.kernel.org/all/20261022051654.79224-1-kmehltretter@gmail.com/ Assisted-by: LLM Hongyan Xia (1): arm64: Always inline raw preempt count updates Karl Mehltretter (11): sched: Split preempt-count bookkeeping from raw updates lockdep: Use raw access for pinned hardirq state entry: Add the pre-counted ordinary-hardirq entry/exit contract entry: Skip inactive IRQ-return reschedule calls context_tracking: Split IRQ-exit preparation from the EQS transition lockdep: Prepare IRQ-on state from a hardirq return tail entry: Carry ordinary-hardirq provenance through kernel return entry: Classify ordinary hardirq return-tail work as hardirq context arm64: Use the pre-counted hardirq lifecycle Documentation: entry: Describe the pre-counted hardirq lifecycle locking/selftest: Exercise hardirq return-tail preparation Will Deacon (1): arm64: percpu: Annotate __kern_my_cpu_offset() as '__always_inline' Documentation/core-api/entry.rst | 89 +++++++++++-- arch/arm64/include/asm/percpu.h | 2 +- arch/arm64/include/asm/preempt.h | 6 +- arch/arm64/kernel/entry-common.c | 34 +++-- include/linux/context_tracking_irq.h | 32 ++++- include/linux/hardirq.h | 33 +++++ include/linux/interrupt.h | 2 +- include/linux/irq-entry-common.h | 130 +++++++++++++++++-- include/linux/irqentry_hardirq.h | 81 ++++++++++++ include/linux/irqflags.h | 14 ++- kernel/context_tracking.c | 78 +++++++++--- kernel/entry/common.c | 45 ++++++- kernel/locking/lockdep.c | 49 +++++--- kernel/sched/core.c | 101 +++++++++++++-- kernel/softirq.c | 181 +++++++++++++++++++++++---- lib/locking-selftest.c | 53 ++++++++ 16 files changed, 828 insertions(+), 102 deletions(-) create mode 100644 include/linux/irqentry_hardirq.h base-commit: d135ab453a7400a34930bdda1ef4bdc8acfac80e -- 2.39.5 (Apple Git-154)