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[2.155.41.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa813d2950sm4897195e9.8.2026.10.28.10.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 10:11:24 -0700 (PDT) From: =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= To: shawn.lin@rock-chips.com Cc: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, manivannan.sadhasivam@oss.qualcomm.com, bhelgaas@google.com, robh@kernel.org, heiko@sntech.de, dlemoal@kernel.org, linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, iav@iav.lv Subject: Re: [PATCH v3] PCI: rockchip: Don't lengthen PERST# when power is already valid Date: Wed, 28 Oct 2026 17:11:22 +0000 Message-ID: <20261028171122.3422629-1-ehbello@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <95aeecc0-2794-4cc6-a635-5c042afc1405@rock-chips.com> References: <20261028005603.2399220-1-ehbello@gmail.com> <20261028015923.2436122-1-ehbello@gmail.com> <95aeecc0-2794-4cc6-a635-5c042afc1405@rock-chips.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261028_101127_856930_DBC6549E X-CRM114-Status: GOOD ( 16.09 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, 28 Oct 2026 02:21:14 +0000, Shawn Lin wrote: > Was it possible to add a DT property for configurable delay? I came > across several EPs need quite a longer wait time, so add it in the > vendor tree for dwc-based IP[1]. That could be applied here to slove > your cases and others', and might avoid regression. > > [1] > https://github.com/rockchip-linux/kernel/blob/develop-6.12/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L865 Thanks -- that is a better shape than mine, and I will do it. I will mirror the vendor driver: rockchip,perst-inactive-ms for the pulse, and rockchip,s2r-perst-inactive-ms for the resume path, since the two paths want different values here as well. One thing I would rather ask than guess: should the default stay at PCIE_T_PVPERL_MS, with affected boards setting the property, or should the default be the spec minimum, with the property there for endpoints that need longer? What makes me ask is where T_PVPERL is measured from. It runs from power stable to PERST# inactive, so on a board whose slot rails are regulator- always-on it is already satisfied seconds before the driver touches the GPIO, and the 100 ms then only widens the pulse. The one pulse-width floor the spec gives is T_PERST, 100 us. On my board that difference decides whether the JMB585 answers config reads at all: 0 of 5 boots with a 100 ms pulse, 5 of 5 with a short one, with the power-settling time held constant across both. Keeping the current default is the safer change and I am happy to do that. I would just rather we did it knowingly, instead of carrying a number that was only ever right for boards which power the slot at the moment they assert PERST#. Secondary question: do you want the vendor-prefixed names, or would the DT binding maintainers prefer something generic, given the timing comes from the CEM spec rather than from Rockchip?