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[2.155.41.158]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebc39a8sm30601206f8f.11.2026.10.28.10.31.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 10:31:10 -0700 (PDT) From: =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= To: iav@iav.lv Cc: shawn.lin@rock-chips.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, manivannan.sadhasivam@oss.qualcomm.com, bhelgaas@google.com, robh@kernel.org, heiko@sntech.de, dlemoal@kernel.org, linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] PCI: rockchip: Skip the Tpvperl wait when power is already valid Date: Wed, 28 Oct 2026 17:31:08 +0000 Message-ID: <20261028173108.3457165-1-ehbello@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261028-h64-tpvperl-ab-skip@iav.lv> References: <20260911211559.207990-1-ehbello@gmail.com> <179196286749.38040.5597453767131590054.b4-reply@b4> <20261016-h64-pcie-resume-tpvperl@iav.lv> <20261028005548.2399155-1-ehbello@gmail.com> <20261028-h64-tpvperl-ab-skip@iav.lv> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261028_103114_183572_FD5DC1F9 X-CRM114-Status: GOOD ( 12.70 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-4.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, 28 Oct 2026 05:10:00 +0000, Igor Velkov wrote: > Since the next version keeps the full wait on resume, it no longer > changes the resume path, so I'll skip the A/B and test that version > on Helios64 instead: boots plus s2idle cycles, results in reply to it. Thank you -- that coverage is worth a lot, but hold off a little, because the shape is changing again. Shawn Lin has asked for a DT property for the PERST# pulse rather than a decision taken in the driver, matching rockchip,perst-inactive-ms and rockchip,s2r-perst-inactive-ms in the vendor dwc driver, and I have agreed. So the version to test is that one, not the probe-only patch I was about to send. Whether the default changes or stays at PCIE_T_PVPERL_MS is still open, so I will put the DT snippet to set on a Helios64 in the cover letter instead of leaving it to guesswork.