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[194.152.27.116]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71a4d3cesm23362309f8f.7.2026.11.02.09.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 09:03:30 -0800 (PST) From: Jernej Skrabec To: Mauro Carvalho Chehab , Hans Verkuil Cc: Maxime Ripard , Paul Kocialkowski , Greg Kroah-Hartman , Chen-Yu Tsai , Samuel Holland , Nicolas Dufresne , linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 09/10] staging: media: cedrus: h616: use the 256-bit DDR mode Date: Mon, 2 Nov 2026 18:03:02 +0100 Message-ID: <20261102170303.1973892-10-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261102170303.1973892-1-jernej.skrabec@gmail.com> References: <20261102170303.1973892-1-jernej.skrabec@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261102_090333_438339_778D2DAA X-CRM114-Status: GOOD ( 21.00 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 With the DDR mode in VE_MODE set to 128-bit, which the driver uses on all SoCs, the H616 H.264 engine reads corrupted reference chroma, while luma is fine. H.264 and VP8 P frames come out with bit-exact luma, but with about 22 dB PSNR chroma. H.265 and MPEG-2 are unaffected. The vendor library selects the DDR mode based on the VE IC version. It uses the 256-bit mode without the 2 MiB reconstruction write mode on the H616, and keeps the 128-bit mode with the 2 MiB reconstruction write mode on older SoCs, like the H6. Doing the same on the H616 makes all codecs bit-exact (tested with BA_MW_D, CABA2_Sony_E, vp80-00-comprehensive-002, AMP_A_Samsung_7 and MEI.stream16). Make the VE_MODE DDR settings a variant property and add an H616 variant, which uses the 256-bit mode. Replace the FIXME about the DDR mode with a description of what the vendor library does. Fixes: 1f24d4307515 ("staging: media: sunxi: cedrus: add H616 variant") Signed-off-by: Jernej Skrabec --- drivers/staging/media/sunxi/cedrus/cedrus.c | 14 +++++++++++++- drivers/staging/media/sunxi/cedrus/cedrus.h | 2 ++ drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 14 ++++++++++---- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index 756243795de8..2bbc79b44f99 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -27,6 +27,7 @@ #include "cedrus_video.h" #include "cedrus_dec.h" #include "cedrus_hw.h" +#include "cedrus_regs.h" /* * The hardware decodes whatever picture size the bitstream headers describe. @@ -697,6 +698,17 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = { .mod_rate = 600000000, }; +static const struct cedrus_variant sun50i_h616_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED | + CEDRUS_CAPABILITY_MPEG2_DEC | + CEDRUS_CAPABILITY_H264_DEC | + CEDRUS_CAPABILITY_H265_DEC | + CEDRUS_CAPABILITY_H265_10_DEC | + CEDRUS_CAPABILITY_VP8_DEC, + .mod_rate = 600000000, + .ve_mode_ddr = VE_MODE_DDR_MODE_BW_256, +}; + static const struct of_device_id cedrus_dt_match[] = { { .compatible = "allwinner,sun4i-a10-video-engine", @@ -744,7 +756,7 @@ static const struct of_device_id cedrus_dt_match[] = { }, { .compatible = "allwinner,sun50i-h616-video-engine", - .data = &sun50i_h6_cedrus_variant, + .data = &sun50i_h616_cedrus_variant, }, { /* sentinel */ } }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index a523b56a9b8c..d28fe91562d1 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -181,6 +181,7 @@ struct cedrus_dec_ops { struct cedrus_variant { unsigned int capabilities; unsigned int mod_rate; + u32 ve_mode_ddr; }; struct cedrus_dev { @@ -204,6 +205,7 @@ struct cedrus_dev { struct reset_control *rstc; unsigned int capabilities; + u32 ve_mode_ddr; struct delayed_work watchdog_work; }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c index 444fb53878d1..b66d855daaf8 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -36,11 +36,16 @@ int cedrus_engine_enable(struct cedrus_ctx *ctx) u32 reg = 0; /* - * FIXME: This is only valid on 32-bits DDR's, we should test - * it on the A13/A33. + * The DDR mode depends on the SoC. Like the vendor library, use the + * 128-bit mode with the 2 MiB reconstruction write mode, unless the + * variant says otherwise. */ - reg |= VE_MODE_REC_WR_MODE_2MB; - reg |= VE_MODE_DDR_MODE_BW_128; + if (ctx->dev->ve_mode_ddr) { + reg |= ctx->dev->ve_mode_ddr; + } else { + reg |= VE_MODE_REC_WR_MODE_2MB; + reg |= VE_MODE_DDR_MODE_BW_128; + } switch (ctx->src_fmt.pixelformat) { case V4L2_PIX_FMT_MPEG2_SLICE: @@ -254,6 +259,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) return -EINVAL; dev->capabilities = variant->capabilities; + dev->ve_mode_ddr = variant->ve_mode_ddr; irq_dec = platform_get_irq(dev->pdev, 0); if (irq_dec <= 0) -- 2.43.0