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Mon, 02 Nov 2026 09:19:12 -0800 (PST) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a429467cdsm36978047eec.19.2026.11.02.09.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 09:19:11 -0800 (PST) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Frank Wunderlich , Peter Geis , Junhao Xie , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v2 4/6] arm64: dts: rockchip: fix GMAC clock parent on Photonicat Date: Tue, 3 Nov 2026 01:18:36 +0800 Message-ID: <20261102171838.2958552-5-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261102171838.2958552-1-coiaprant@gmail.com> References: <20261102171838.2958552-1-coiaprant@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261102_091912_872753_16046211 X-CRM114-Status: GOOD ( 14.70 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The RGMII WAN port on the Ariaboard Photonicat uses SCLK_GMAC1 as the GMAC main clock and SCLK_GMAC1_RX_TX as the RGMII speed clock. Only the parent of SCLK_GMAC1_RX_TX is set, so SCLK_GMAC1 keeps whatever parent the bootloader or the hardware reset left. Set the parent of SCLK_GMAC1 to CLK_MAC1_2TOP explicitly, so the GMAC main clock always uses the internal source and does not depend on the bootloader state. The rate assignment is unchanged: SCLK_GMAC1_RX_TX keeps its rate unset, SCLK_GMAC1 stays at 125 MHz. Fixes: ba124e06ce7b ("arm64: dts: rockchip: add dts for Ariaboard Photonicat RK3568") Signed-off-by: Coia Prant --- arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts index b719d5b661c43..7e0a2ab829209 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -285,7 +285,7 @@ &gmac0 { /* Motorcomm YT8521SC WAN port */ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy>; -- 2.47.3