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Tue, 03 Nov 2026 08:37:19 -0800 (PST) Received: from threads.localdomain ([90.254.187.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71a4d3e9sm29044772f8f.6.2026.11.03.08.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 08:37:18 -0800 (PST) From: Lucas Tanure To: xianwei.zhao@amlogic.com, Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/7] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac Date: Tue, 3 Nov 2026 16:37:10 +0000 Message-ID: <20261103163715.385394-3-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261103163715.385394-1-tanure@linux.com> References: <20261103163715.385394-1-tanure@linux.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261103_083721_378861_6C692E85 X-CRM114-Status: GOOD ( 13.23 ) X-Spam-Score: -0.8 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The T7 has the same ethernet glue as the G12A but needs two clocks of its own. The controller reaches memory through a pipeline stage with its own gate; nothing else claims it, so it is switched off as unused and transfers never finish. The glue registers sit in a block clocked together with the MDIO multiplexer, which probes after the controller has programmed them: the writes are lost and the port keeps the bootloader's delays. So the T7 gets its own clock list, without the timing adjustment clock it never uses. Its delays follow ethernet-controller.yaml: the PHY adds the 2ns, and only the receive delay line offers fine tuning, so only rx-internal-delay-ps is valid here. Assisted-by: LLM Signed-off-by: Lucas Tanure --- .../bindings/net/amlogic,meson-dwmac.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index e769c9bb70d8..6de013e3e8f6 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -23,6 +23,7 @@ select: - amlogic,meson-gxbb-dwmac - amlogic,meson-axg-dwmac - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac required: - compatible @@ -57,6 +58,59 @@ allOf: - const: clkin1 - const: timing-adjustment + - if: + properties: + compatible: + contains: + const: amlogic,t7-dwmac + then: + properties: + clocks: + items: + - description: GMAC main clock + - description: First parent clock of the internal mux + - description: Second parent clock of the internal mux + - description: + clock of the pipeline stage inserted in the bus path between + the controller and the DRAM. Without it, the controller cannot + complete DMA transfers. + - description: + clock of the register block holding PRG_ETH0 and PRG_ETH1. + Without it, the block reads as zero and ignores writes. + + clock-names: + items: + - const: stmmaceth + - const: clkin0 + - const: clkin1 + - const: pipeline + - const: pclk + + # The PHY adds the 2ns RGMII delays, see ethernet-controller.yaml. + # The RX delay line of this glue is fine tuning in 200ps steps, + # added on top of what phy-mode describes. The TX side has no fine + # tuning: its only step is a quarter of the clock period, the full + # 2ns at 1Gbit/s, so the TX property is not accepted. + tx-internal-delay-ps: false + + # Deprecated: new SoCs use the standard *-internal-delay-ps + # properties instead. + amlogic,tx-delay-ns: false + amlogic,rx-delay-ns: false + + # Delay definitions for Meson8b and newer + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8b-dwmac + - amlogic,meson8m2-dwmac + - amlogic,meson-gxbb-dwmac + - amlogic,meson-axg-dwmac + - amlogic,meson-g12a-dwmac + then: + properties: amlogic,tx-delay-ns: enum: [0, 2, 4, 6] default: 2 @@ -106,6 +160,7 @@ allOf: contains: enum: - amlogic,meson-g12a-dwmac + - amlogic,t7-dwmac then: properties: rx-internal-delay-ps: @@ -142,6 +197,10 @@ properties: - items: - const: amlogic,meson6-dwmac - const: snps,dwmac + - items: + - const: amlogic,t7-dwmac + - const: snps,dwmac-5.10a + - const: snps,dwmac reg: items: -- 2.56.0