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Thu, 05 Nov 2026 02:03:30 -0800 (PST) Received: from threads.localdomain ([90.254.187.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b43342773esm53455775e9.4.2026.11.05.02.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 02:03:30 -0800 (PST) From: Lucas Tanure To: xianwei.zhao@amlogic.com, Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/7] net: stmmac: dwmac-meson8b: follow the generic RGMII delay rules on the T7 Date: Thu, 5 Nov 2026 10:03:19 +0000 Message-ID: <20261105100322.37816-5-tanure@linux.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261105100322.37816-1-tanure@linux.com> References: <20261105100322.37816-1-tanure@linux.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261105_020332_490383_C324E820 X-CRM114-Status: GOOD ( 18.80 ) X-Spam-Score: -0.8 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The delay code reads phy-mode as the list of delays this glue has to add, falls back to a 2ns transmit delay when no property asks for one, and takes the vendor delay properties. ethernet-controller.yaml says the opposite: the PHY adds the 2ns delays, and the MAC properties only hold small fine tuning added on top. Every board in the tree depends on the old reading, so it stays as it is. No T7 board uses this glue yet, so the T7 gets a path of its own that follows the generic rules: the receive delay line is fine tuning in 200ps steps, and the transmit side, a quarter-period phase step, offers none, so the transmit property is refused. Assisted-by: LLM Signed-off-by: Lucas Tanure --- .../ethernet/stmicro/stmmac/dwmac-meson8b.c | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index 450f7b4b29a6..c8bd15b6780b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -80,6 +80,7 @@ struct meson8b_dwmac; struct meson8b_dwmac_data { int (*set_phy_mode)(struct meson8b_dwmac *dwmac); + int (*init_delays)(struct meson8b_dwmac *dwmac); bool has_prg_eth1_rgmii_rx_delay; bool has_pipeline_clk; }; @@ -338,6 +339,41 @@ static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac) return 0; } +/* + * The T7 follows ethernet-controller.yaml: the PHY adds the 2ns RGMII + * delays and this glue only fine tunes the RX clock on top of what + * phy-mode describes. Its TX clock has no fine tuning, the only step is + * a quarter of the clock period, so the TX property is refused, and so + * are the vendor properties of the older SoCs. + */ +static int meson_t7_init_delays(struct meson8b_dwmac *dwmac) +{ + struct device_node *np = dwmac->dev->of_node; + u32 cfg_rxclk_dly = 0; + + if (of_property_present(np, "tx-internal-delay-ps") || + of_property_present(np, "amlogic,tx-delay-ns") || + of_property_present(np, "amlogic,rx-delay-ns")) + return dev_err_probe(dwmac->dev, -EINVAL, + "only rx-internal-delay-ps is supported, the PHY adds the RGMII delays\n"); + + if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) + cfg_rxclk_dly = FIELD_PREP(PRG_ETH1_CFG_RXCLK_DLY, + dwmac->rx_delay_ps / 200); + else if (dwmac->rx_delay_ps) + return dev_err_probe(dwmac->dev, -EINVAL, + "rx-internal-delay-ps needs an RGMII phy-mode\n"); + + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK | + PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP | + PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW, 0); + + meson8b_dwmac_mask_bits(dwmac, PRG_ETH1, PRG_ETH1_CFG_RXCLK_DLY, + cfg_rxclk_dly); + + return 0; +} + static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) { int ret; @@ -452,7 +488,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) "missing pipeline clock\n"); } - ret = meson8b_init_rgmii_delays(dwmac); + ret = dwmac->data->init_delays(dwmac); if (ret) return ret; @@ -475,21 +511,25 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) static const struct meson8b_dwmac_data meson8b_dwmac_data = { .set_phy_mode = meson8b_set_phy_mode, + .init_delays = meson8b_init_rgmii_delays, .has_prg_eth1_rgmii_rx_delay = false, }; static const struct meson8b_dwmac_data meson_axg_dwmac_data = { .set_phy_mode = meson_axg_set_phy_mode, + .init_delays = meson8b_init_rgmii_delays, .has_prg_eth1_rgmii_rx_delay = false, }; static const struct meson8b_dwmac_data meson_g12a_dwmac_data = { .set_phy_mode = meson_axg_set_phy_mode, + .init_delays = meson8b_init_rgmii_delays, .has_prg_eth1_rgmii_rx_delay = true, }; static const struct meson8b_dwmac_data meson_t7_dwmac_data = { .set_phy_mode = meson_axg_set_phy_mode, + .init_delays = meson_t7_init_delays, .has_prg_eth1_rgmii_rx_delay = true, .has_pipeline_clk = true, }; -- 2.56.0