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bh=IAD0JHK5u0AjR1SS9NS5jBII24VCj84wL7W/E6MbcFQ=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1793883924; v=1; x=1794488724; b=cXqu3Qe8dxF1bgYAdO4vcQt1eL4M7qpY6hic36BzFVEzq4v7OYmAduvOVyN9DNbe/tS7G4F5 KPEqWQ3AXRptH9iJyPVPBPOu2iO0EZR5vTio2OmvqPUmvbZXSH1KbrxoDw0mv9PbuiLTRmRizKe TDyB58FnCCFNbv4DEZfeZm24= X-Envelope-To: linux-arm-kernel@lists.infradead.org Received: by smtp.migadu.com with ESMTPS id 981a1b1030f162c4; Thu, 05 Nov 2026 13:05:23 +0000 X-Mizu-Trace-ID: 981a1b1030f162c4 X-Migadu-Flow: FLOW_OUT From: Fuad Tabba To: Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Joey Gouly , Suzuki K Poulose , Zenghui Yu , Steffen Eiden , Catalin Marinas , Will Deacon , Mark Rutland , Vincent Donnefort , Fuad Tabba , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] KVM: arm64: Allow protected VMs to use SVE Date: Thu, 5 Nov 2026 13:04:56 +0000 Message-ID: <20261105130456.1617185-5-fuad.tabba@linux.dev> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261105130456.1617185-1-fuad.tabba@linux.dev> References: <20261105130456.1617185-1-fuad.tabba@linux.dev> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261105_130525_627981_17504DC6 X-CRM114-Status: GOOD ( 15.95 ) X-Spam-Score: -0.9 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Now that EL2 owns a protected vCPU's SVE state and advertises ID_AA64ZFR0_EL1, allow KVM_CAP_ARM_SVE for a protected VM, which lets KVM_ARM_VCPU_INIT take KVM_ARM_VCPU_SVE. A protected guest's SVE access trap injects an UNDEF. An SVE instruction takes the SVE trap rather than the FP one, so a guest whose first vector instruction is an SVE one would get an UNDEF instead of the lazy FP switch. Handle the SVE trap as the FP trap is: kvm_handle_pvm_fpsimd() switches the state for a vCPU with SVE and still injects the UNDEF for one without. Update the documentation to match. Signed-off-by: Fuad Tabba --- Documentation/virt/kvm/arm/pkvm.rst | 6 +++--- arch/arm64/include/asm/kvm_pkvm.h | 1 + arch/arm64/kvm/hyp/nvhe/switch.c | 1 + arch/arm64/kvm/hyp/nvhe/sys_regs.c | 2 -- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/virt/kvm/arm/pkvm.rst b/Documentation/virt/kvm/arm/pkvm.rst index b75bb8ad6f26d..163aa01ac5067 100644 --- a/Documentation/virt/kvm/arm/pkvm.rst +++ b/Documentation/virt/kvm/arm/pkvm.rst @@ -134,9 +134,9 @@ A protected VM boots from a single primary vCPU. Before the first * Set the primary vCPU's boot state with ``KVM_SET_ONE_REG``: the kernel entry address in ``PC`` and the DTB pointer in ``x0``. -``PC`` and ``x0`` are the only registers EL2 takes from the host. Other -pre-run writes are accepted, but the guest starts from the state the -hypervisor resets it to. +``PC``, ``x0`` and the SVE vector lengths (``KVM_REG_ARM64_SVE_VLS``) are +the only registers EL2 takes from the host. Other pre-run writes are +accepted, but the guest starts from the state the hypervisor resets it to. Secondary vCPUs are started by the guest itself through PSCI ``CPU_ON`` (see `Power state`_), which supplies their entry point and context ID. diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm_pkvm.h index fd042d2b54624..5f1b3308b42e1 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -40,6 +40,7 @@ static inline bool kvm_pkvm_ext_allowed(struct kvm *kvm, long ext) case KVM_CAP_MAX_VCPU_ID: case KVM_CAP_MSI_DEVID: case KVM_CAP_ARM_VM_IPA_SIZE: + case KVM_CAP_ARM_SVE: case KVM_CAP_ARM_PTRAUTH_ADDRESS: case KVM_CAP_ARM_PTRAUTH_GENERIC: case KVM_CAP_ONE_REG: diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index 89fb9dd351ad5..0626f4203ba6d 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -230,6 +230,7 @@ static const exit_handler_fn pvm_exit_handlers[] = { [ESR_ELx_EC_WFx] = kvm_handle_pvm_wfx, [ESR_ELx_EC_HVC64] = kvm_handle_pvm_hvc64, [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, + [ESR_ELx_EC_SVE] = kvm_handle_pvm_fpsimd, [ESR_ELx_EC_FP_ASIMD] = kvm_handle_pvm_fpsimd, [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index e6bbc897cd7b1..0ddddf957f5ab 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -502,8 +502,6 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = { ID_UNALLOCATED(7,6), ID_UNALLOCATED(7,7), - /* Scalable Vector Registers are restricted. */ - HOST_HANDLED(SYS_ICC_PMR_EL1), RAZ_WI(SYS_ERRIDR_EL1), -- 2.47.3