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[2001:1c00:1106:900:938c:4ed8:a3bb:93f]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b57feb668bsm886834a12.13.2026.11.05.12.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 12:38:18 -0800 (PST) From: Mario Behn To: Mark Brown , Michal Simek Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mario Behn Subject: [PATCH v1 0/2] spi: zynq-qspi: use a flash larger than 16 MiB Date: Thu, 5 Nov 2026 21:37:32 +0100 Message-ID: <20261105203734.979168-1-mario.behn@gmail.com> X-Mailer: git-send-email 2.53.0 X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261105_123823_092137_7B80143A X-CRM114-Status: GOOD ( 11.93 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The Zynq-7000 QSPI controller sends at most 3 address bytes. spi-nor needs 4-byte addresses for a flash larger than 16 MiB, so on a board with a 32 MiB W25Q256 (the ADALM-PLUTO+ has one) the probe fails with -EINVAL and no mtd device appears. These two patches keep the flash in 3-byte mode and handle an operation with a 4-byte address inside the controller driver, through the flash's Extended Address Register (EAR): write enable, write EAR with addr >> 24, the operation in its 3-byte form, then the EAR back to 0. The EAR is 0 between operations, so a warm reset leaves the BootROM and U-Boot in bank 0. Patch 1 makes the flash readable (every other operation is refused). Patch 2 adds program and erase, which need the write enable again after the EAR write, a check of the bank register before the operation, and waiting for the flash to be idle before the EAR is restored. Tested on an ADALM-PLUTO+ (Zynq-7010, W25Q256, JEDEC id ef4019) with v7.3 plus these patches: - the four partitions (mtd0 to mtd3, the last one 30 MiB and crossing the 16 MiB bank boundary) read back with the same md5 as on a vendor 6.12 kernel that handles the 4-byte addresses in spi-nor; - the U-Boot environment in mtd1 is written with fw_setenv, survives a reboot and is read back; - one 64 KiB block in bank 1: erase, program a random pattern, read back (equal), restore; - 14 MiB (224 erase blocks) in bank 1: erase, program, read back (equal), restore; about 110 s each way; - a 26 MB firmware image written into the 30 MiB partition from the running system and verified byte for byte, after which the board boots from QSPI; - no driver error in the kernel log during any of it. Not tested: other flash chips, boards with a flash on another chip select, or the quad program path with a flash that is not a W25Q256. Mario Behn (2): spi: zynq-qspi: read flash above 16 MiB via the extended address register spi: zynq-qspi: program and erase flash above 16 MiB via the EAR drivers/spi/spi-zynq-qspi.c | 1 file changed