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Sun, 8 Nov 2026 02:02:11 -0500 (EST) From: Jiaxing Hu To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org, p.zabel@pengutronix.de, ogabbay@kernel.org, zhangqing@rock-chips.com Cc: royalnet026@gmail.com, abel.vesa@oss.qualcomm.com, sebastian.reichel@collabora.com, sidong.yang@furiosa.ai, u.kleine-koenig@baylibre.com, chaoyi.chen@rock-chips.com, shawn.lin@rock-chips.com, finley.xiao@rock-chips.com, diederik@cknow-tech.com, alchark@flipper.net, leonard@lausen.nl, jeff.hugo@oss.qualcomm.com, rfoss@kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiaxing Hu Subject: [PATCH v16 10/16] pmdomain: rockchip: cycle an optional power-domain reset on power-on Date: Sun, 8 Nov 2026 19:59:11 +1300 Message-ID: <20261108065917.135194-11-gahing@gahingwoo.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261108065917.135194-1-gahing@gahingwoo.com> References: <20261108065917.135194-1-gahing@gahingwoo.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261107_230224_821917_25A8B688 X-CRM114-Status: GOOD ( 19.50 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 The bus interface of some power domains can be left in an undefined state after power-on. On the RK3576 NPU this shows up as a hang on the first register access after power-on. Resetting the power domain once makes access work again. When the power domain node has a reset, the driver gets it and cycles it after releasing the idle request and before restoring QoS. This is optional. Power domains without a reset are not affected. Signed-off-by: Jiaxing Hu Reviewed-by: Abel Vesa Reviewed-by: Heiko Stuebner --- drivers/pmdomain/rockchip/pm-domains.c | 33 +++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index e3cc60fa2277..0f4ea5471792 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -103,6 +104,7 @@ struct rockchip_pm_domain { struct clk_bulk_data *clks; struct device_node *node; struct regulator *supply; + struct reset_control *reset; }; struct rockchip_pmu { @@ -688,6 +690,21 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) if (ret < 0) goto out; + /* + * Optional: some domains need their reset cycled once power + * is on. This goes BEFORE the settle delay, not after: a + * domain that asks for both is asking to settle before the + * QoS registers answer, and a reset deasserted after the + * delay would leave nothing between it and the QoS writes. + * On RK3576 the reset being cycled is the NPU core's bus + * interface, which is what those writes go through. + */ + if (pd->reset) { + reset_control_assert(pd->reset); + usleep_range(10, 20); + reset_control_deassert(pd->reset); + } + /* Some domains need to settle before the QoS registers answer. */ if (pd->info->delay_us) udelay(pd->info->delay_us); @@ -873,6 +890,14 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, if (error) goto err_put_clocks; + pd->reset = of_reset_control_get_optional_exclusive(node, NULL); + if (IS_ERR(pd->reset)) { + error = dev_err_probe(pmu->dev, PTR_ERR(pd->reset), + "%pOFn: failed to get reset\n", node); + pd->reset = NULL; + goto err_unprepare_clocks; + } + pd->num_qos = of_count_phandle_with_args(node, "pm_qos", NULL); @@ -943,11 +968,13 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, clk_bulk_unprepare(pd->num_clks, pd->clks); err_put_clocks: clk_bulk_put(pd->num_clks, pd->clks); + reset_control_put(pd->reset); return error; } static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) { + struct reset_control *reset; int ret; /* @@ -962,11 +989,15 @@ static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) clk_bulk_unprepare(pd->num_clks, pd->clks); clk_bulk_put(pd->num_clks, pd->clks); - /* protect the zeroing of pm->num_clks */ + /* protect the zeroing of pd->num_clks and pd->reset */ mutex_lock(&pd->pmu->mutex); pd->num_clks = 0; + reset = pd->reset; + pd->reset = NULL; mutex_unlock(&pd->pmu->mutex); + reset_control_put(reset); + /* devm will free our memory */ } -- 2.43.0