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Tue, 10 Nov 2026 07:35:24 -0800 (PST) Received: from dev.Default ([86.127.229.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba01fe2cb2sm67511805e9.3.2026.11.10.07.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 07:35:23 -0800 (PST) From: Agustin Santiago Isasmendi To: =?UTF-8?q?Stefan=20D=C3=B6singer?= , Navid Ghahremani Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, krzk@kernel.org Subject: Re: [PATCH v2 00/24] ARM: zte: Add support for Sanechips ZX279128S and ZTE ZXHN H3600 Date: Tue, 10 Nov 2026 16:35:22 +0100 Message-Id: <20261110153522.1620088-1-isasmendi.agus@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261106190828.3823287-1-isasmendi.agus@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_073526_700388_73ED0900 X-CRM114-Status: GOOD ( 19.22 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Stefan, On Sun, 8 Nov 2026, Stefan Dösinger wrote: > However, Arnd Bergmann didn't like the hack and it looks like we don't > understand what exactly is going on, so they agreed to postpone this > particular issue for now (see follow-up replies in the linked thread). If you > have further ideas what ZTE got wrong in the hardware and what kind of > workaround they use that would be helpful Thanks, I had missed that thread. The RFC I mentioned was the same lock, so I will not send it. Here is what I know so far, from my H3600 on Navid's v2. What ZTE does (from their 4.1.25 kernel binary): l2x0_lock is taken around every line write of the L2C range operations and around the Cache Sync, and around every register read of their mt7915 driver (through an exported fixed_pci_read_u32()). A later module only makes the lock finer: the range ops drop it every 2 KiB, and a pending PCIe read makes them drop it early. I found no chicken bit: their L2C setup matches ours and their PCIe init has no such setting. What goes wrong: a PCIe read on one CPU deadlocks against an L2C-310 line operation by PA or a Cache Sync on the other. The TRM (DDI 0246H, 3.3.10) says those operations stall the L2C slave ports until they complete, and here the PCIe read apparently cannot complete meanwhile. 3 boots x 8 minutes of WiFi traffic each: no workaround hang 3/3 maxcpus=1 ok 3/3 arm,outer-sync-disable hang 3/3 lock around the Cache Sync only hang 3/3 lock around the range ops only hang 3/3 lock on the L2C side only, reads unlocked hang 3/3 lock on both sides (as ZTE) ok 3/3 dma-coherent firmware load fails So PCIe DMA is not coherent and the maintenance has to stay. A possible way forward: Arnd's fallback of SMP with the L2 off works, no hang in 3 boots x 8 minutes (75 transfers). It cannot be done from the DT today, because l2x0_of_init() ignores status = "disabled"; I had to change the compatible for the test. So I would suggest: - a small patch so that l2x0_of_init() honours the status property (no in-tree PL310 node is disabled, so nothing else changes); - Navid's DT disables the L2C, so mainline is stable with WiFi; - the lock stays downstream in OpenWrt until there is a better fix. I haven't measured the cost of the L2 off properly yet; I can do that if this direction sounds reasonable. Cheers, Agustin