From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB03660A260E for ; Tue, 10 Nov 2026 17:22:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=yoFS0i1H DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Unsubscribe-Post: List-Owner; bh=th1SQ93PTn4zjaYRKsFKLnVzC7ZFjCtO0N4lCexiRk0=; b=yoFS0i1HuPG865 j9avTv2Tg3sR6VybQimRZ6sVaBZV6eUNJ8g0lwP1SZzrbdby2cAEsIecmQa40JbBY7doQhmXozfLP NpLQeBzPiPdGF/RZffK5e99Lc/Y46Ph/Q5yXlcdWzEuUD5yTTz4nMPXSbHxbPJf9s/wwUNL8rtrcN UAlt+4QP5cwfin9v07b0CpAZp/YPzcvB3fD8FUS54U4T/2AcNCdOxw7CrX22vZFzhjaG2LfKLDCy9 s/NPPZ9v4Yt/lLzdom+rtEYeabw1EDPfFbq6RB9qM6kF2Y2VAJm4rJ38ukD8z0CjJBxr10BE2phgm LMLtuDeTGmrGXNbVgdew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xQpXq-00000004fbM-2Ud5; Tue, 10 Nov 2026 17:22:06 +0000 Received: from nbd.name ([46.4.11.11]) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xQpXj-00000004fVt-47wW; Tue, 10 Nov 2026 17:22:02 +0000 Received: from [2a04:4540:1403:9bfc:b113:5373:d0ec:2ad1] (helo=bertha10..) by ds12 with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1xQpXU-001C99-2m; Tue, 10 Nov 2026 18:21:44 +0100 From: John Crispin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Christian Marangi , devicetree@vger.kernel.org, Felix Fietkau , lei.dong@airoha.com, Linqi.zhang@airoha.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Rajeev.kumar@airoha.com, upstream@airoha.com, Weifeng.xu@airoha.com, zhengping.zhang@airoha.com Subject: [PATCH 2/3] arm64: dts: airoha: add AN7589 SoC dtsi Date: Tue, 10 Nov 2026 18:21:42 +0100 Message-Id: <20261110172143.296304-3-john@phrozen.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261110172143.296304-1-john@phrozen.org> References: <20261110172143.296304-1-john@phrozen.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_092200_023716_D4247D90 X-CRM114-Status: GOOD ( 12.26 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Add the device tree for the Airoha AN7589 SoC. It describes the four Cortex-A73 cores, which the firmware brings up over PSCI, the GICv3, the architected timer and the console UART. The UART runs from a fixed 1.8432 MHz clock, so the console works before the SCU clock controller probes. The remaining blocks follow later. Signed-off-by: John Crispin --- arch/arm64/boot/dts/airoha/an7589.dtsi | 134 +++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/an7589.dtsi diff --git a/arch/arm64/boot/dts/airoha/an7589.dtsi b/arch/arm64/boot/dts/airoha/an7589.dtsi new file mode 100644 index 000000000000..c0153a00c88a --- /dev/null +++ b/arch/arm64/boot/dts/airoha/an7589.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x200000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-level = <2>; + cache-unified; + }; + }; + + clk1843200: clock-1843200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1843200>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x0c000000 0x0 0x40000>, + <0x0 0x0c080000 0x0 0x200000>, + <0x0 0x0c400000 0x0 0x2000>, + <0x0 0x0c410000 0x0 0x1000>, + <0x0 0x0c420000 0x0 0x1000>; + interrupts = ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&clk1843200>; + }; + }; +}; -- 2.34.1