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[144.49.247.22]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-3b17db3a05csm442533a91.4.2026.11.10.11.07.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Nov 2026 11:07:27 -0800 (PST) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-91eb3a63064so50696386d6.0 for ; Tue, 10 Nov 2026 11:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1794337646; x=1794942446; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=pa6VwfvBf/lmyVIlZAJGW65vNYl8kWvkzCZbBuLoYbU=; b=IuBjkmzJef7jG/0n3QQpHKw4lm5cFhXJeV2KtWGiN9bYScr8ZkWN+DXFMBfWniQNDK QtI15+zD5Le9P//IqPGPtoKUY/4Aaumdacn7DdBRrtg9eNs6qezygvHS5z2IO5RFcTf7 MiV0VXkrgl/lpltV+OrmiCRxagmhce1EBjEFc= X-Forwarded-Encrypted: i=1; AL+hErFekVgIa//srG2TmBQHclbX2ZBLLHSUoqZSr/Yp8EUq1FaONQeEJDTN3CD8jZztvo3qEb8yqaJ8D81PSRxAPURg@lists.infradead.org X-Received: by 2002:a05:6214:e87:b0:91e:b7fd:8ce7 with SMTP id 6a1803df08f44-91f04122ec1mr3192256d6.28.1794337646221; Tue, 10 Nov 2026 11:07:26 -0800 (PST) X-Received: by 2002:a05:6214:e87:b0:91e:b7fd:8ce7 with SMTP id 6a1803df08f44-91f04122ec1mr3191796d6.28.1794337645698; Tue, 10 Nov 2026 11:07:25 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91f046e42a7sm448086d6.31.2026.11.10.11.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 11:07:24 -0800 (PST) From: Florian Fainelli To: bcm-kernel-feedback-list@broadcom.com, Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Florian Fainelli , Russell King , William Zhang , Anand Gore , Kursad Oney , =?iso-8859-2?q?Rafa=B3_Mi=B3ecki?= Cc: Florian Fainelli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 2/3] ARM: bcm: Add CFE SMP support for BCMBCA Date: Tue, 10 Nov 2026 11:07:22 -0800 Message-ID: <20261110190722.2345878-1-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261105-genexis-xg6846-smp-v7-3-rc1-v5-2-4103df2588d3@kernel.org> References: <20261105-genexis-xg6846-smp-v7-3-rc1-v5-0-4103df2588d3@kernel.org> <20261105-genexis-xg6846-smp-v7-3-rc1-v5-2-4103df2588d3@kernel.org> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_110728_881382_6864C56F X-CRM114-Status: GOOD ( 15.33 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Florian Fainelli On Thu, 05 Nov 2026 14:24:47 +0100, Linus Walleij wrote: > The XG6846B CFE bootloader powers up CPU1 and leaves it in a holding pen > waiting for an interrupt. After waking, the stub reads the GPIO > GeneralPurpose register at 0xff800568 and branches to the stored address > in ARM state. The vendor kernel uses this mailbox and a wakeup IPI. > > Implement the brcm,bca-smp CPU enable-method for BCMBCA systems > booted through CFE. > Read the mailbox address from the secondary CPU's cpu-release-addr > property. Map it as device memory, write secondary_startup_arm and > complete the write before sending the wakeup IPI. CPU1 is already > running, so no power or reset sequence is needed. Using the ARM entry > also supports kernels built in Thumb-2 mode. Clear any Thumb function > pointer tag before programming this ARM entry address. > > Register the operations with CPU_METHOD_OF_DECLARE() so the CPU > nodes select CFE bring-up explicitly. Build the BCMBCA machine > description independently of DEBUG_BCMBCA, keeping the debug UART > mapping conditional. The generic ARM startup code retains PSCI priority. > > Suggested-by: William Zhang > Reviewed-by: William Zhang > Signed-off-by: Linus Walleij > --- Applied to https://github.com/Broadcom/stblinux/commits/soc/next, thanks! -- Florian