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Wed, 11 Nov 2026 06:00:07 +0000 (UTC) From: Arun Iyengar via B4 Relay Date: Wed, 11 Nov 2026 06:00:08 +0000 Subject: [PATCH v2 2/8] arm64: dts: allwinner: orangepi-zero2: Let the PHY add the RX delay X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261111-h616-zero2-dt-v2-2-88d8030fc975@gmail.com> References: <20261111-h616-zero2-dt-v2-0-88d8030fc975@gmail.com> In-Reply-To: <20261111-h616-zero2-dt-v2-0-88d8030fc975@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ryan Walklin , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Arun Iyengar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794376807; l=1923; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=hgTnawt6aimtaYNRLXqSLgWoRIBtKR4Hz80cKcd5MZQ=; b=rJDt1Z+hIOmV2HpihY42r8mfiUSAtj5Uw7oj3xkPckWjqYiN3DNOs3d5wkuwFn7Qgnk3xkql1 74YOR/oQxQUBlDDqpowj0gyIg8N53bVNxSijNzHPXZnx5qI5FyA/lUr X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Content-Transfer-Encoding: 7bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: aiyengar1990@gmail.com Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, FREEMAIL_REPLYTO_END_DIGIT,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Arun Iyengar The Orange Pi Zero2 describes its RTL8211F link as "rgmii", with the whole RX clock delay (3100 ps, the maximum the H616 EMAC syscon can add) inserted by the MAC. With "rgmii" the Realtek PHY driver also clears the PHY's own RX delay bit, so RX sampling relies on the MAC delay alone and sits at the edge of the window. On the board this shows up as intermittent boots with a dead receive path, after cold and warm resets alike: the link comes up at 1000/full and frames are transmitted and seen by the peer, but nothing is ever received and the EMAC raises no RX interrupt. All EMAC clock, pinmux, drive strength and syscon registers are the same on good and bad boots. On a bad boot, setting the PHY RX delay bit and clearing the syscon RX delay restores reception at once, without a link reset. Use "rgmii-rxid" (RX delay in the PHY, none in the MAC), as the Orange Pi Zero3 with the same PHY already does, and as the vendor BSP does. The 700 ps MAC TX delay is kept. With this change 10 of 10 cold boots had a working receive path. Fixes: 5a378f9f2b15 ("arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support") Signed-off-by: Arun Iyengar --- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index f2e3300e078a..1fdf2d3c1a87 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -18,9 +18,9 @@ &cpu0 { }; &emac0 { - allwinner,rx-delay-ps = <3100>; allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii"; + /* RX delay is added by the PHY, TX delay by the EMAC */ + phy-mode = "rgmii-rxid"; phy-supply = <®_dcdce>; }; -- 2.55.0