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Wed, 11 Nov 2026 06:00:08 +0000 (UTC) From: Arun Iyengar via B4 Relay Date: Wed, 11 Nov 2026 06:00:12 +0000 Subject: [PATCH v2 6/8] arm64: dts: allwinner: orangepi-zero2: Enable GPU DVFS X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261111-h616-zero2-dt-v2-6-88d8030fc975@gmail.com> References: <20261111-h616-zero2-dt-v2-0-88d8030fc975@gmail.com> In-Reply-To: <20261111-h616-zero2-dt-v2-0-88d8030fc975@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ryan Walklin , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Arun Iyengar X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1794376807; l=990; i=aiyengar1990@gmail.com; s=20261110; h=from:subject:message-id; bh=5MPJQC1S+CHiR8Bt9vkp2Zk5ZwEghmC4r8Nx+9ugUME=; b=87DXPy99NnGEeLVD0wtNkkEfGbzg7aHpEpdfOqHgzEVS3BS5k5Ps5iDC7Mr9PY0dpH9SFYz7H lWW2d9+2J7qDZ/kHX0wHgWiLG6xJ3+HHXqfdQmkVsCYT0/SFBjjg74X X-Developer-Key: i=aiyengar1990@gmail.com; a=ed25519; pk=zXpRgUTrhaFe6jLyPqbBy3ccfkj04w0g2690Wv3mg+0= X-Endpoint-Received: by B4 Relay for aiyengar1990@gmail.com/20261110 with auth_id=1480 X-Original-From: Arun Iyengar Content-Transfer-Encoding: 7bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: aiyengar1990@gmail.com Sender: "linux-arm-kernel" X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, FREEMAIL_REPLYTO_END_DIGIT,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Arun Iyengar The Mali-G31 on the Orange Pi Zero2 runs at a fixed clock. Include the H616 GPU OPP table so that panfrost registers a devfreq device and scales the GPU between 306 and 600 MHz with load. The voltage window of every operating point overlaps the 900 to 990 mV range of the GPU supply (AXP305 DCDCC, mali-supply). Signed-off-by: Arun Iyengar --- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index 719d6dadf7bf..ca78d094c431 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -7,6 +7,7 @@ #include "sun50i-h616-orangepi-zero.dtsi" #include "sun50i-h616-cpu-opp.dtsi" +#include "sun50i-h616-gpu-opp.dtsi" / { model = "OrangePi Zero2"; -- 2.55.0