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[198.27.228.154]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3752060c4b6sm11820704eec.15.2026.11.10.20.19.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Nov 2026 20:19:16 -0800 (PST) From: Ahmad Byagowi To: netdev@vger.kernel.org, vadim.fedorenko@linux.dev, andi.shyti@kernel.org Cc: linux-i2c@vger.kernel.org, Michal Simek , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 2/3] i2c: xiic: add KUnit coverage for register access modes Date: Tue, 10 Nov 2026 20:19:02 -0800 Message-ID: <20261111041904.48916-3-ahmadexp@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261111041904.48916-1-ahmadexp@gmail.com> References: <20261111041904.48916-1-ahmadexp@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_201918_223654_CC0518FC X-CRM114-Status: GOOD ( 22.55 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Exercise the driver's private register accessors with memory-backed registers instead of physical hardware. Cover native byte/halfword and forced 32-bit accesses in both register byte orders, across 22 register offsets. Check payload truncation, high-bit values and neighboring sentinels. These tests do not validate physical bus transaction widths or hardware interrupt behavior. Include the tests in the driver translation unit so no accessors need to become exported interfaces. Require built-in KUnit to avoid a built-in driver depending on a modular test framework. The tests follow the driver into either its built-in image or module. The four parameterized cases passed in an isolated x86-64 QEMU boot with networking disabled and no physical-device passthrough. Tool-origin disclosure, as required by generated-content.rst: Codex was used to implement this test suite, run the KUnit build/boot and draft this changelog, in response to a request for upstream-quality testing. Signed-off-by: Ahmad Byagowi --- MAINTAINERS | 1 + drivers/i2c/busses/Kconfig | 14 ++++ drivers/i2c/busses/i2c-xiic.c | 4 ++ drivers/i2c/busses/tests/i2c_xiic_kunit.c | 88 +++++++++++++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 drivers/i2c/busses/tests/i2c_xiic_kunit.c diff --git a/MAINTAINERS b/MAINTAINERS index 76fb13c87..eb5777316 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4017,6 +4017,7 @@ F: drivers/cpuidle/cpuidle-zynq.c F: drivers/edac/synopsys_edac.c F: drivers/i2c/busses/i2c-cadence.c F: drivers/i2c/busses/i2c-xiic.c +F: drivers/i2c/busses/tests/i2c_xiic_kunit.c F: drivers/mmc/host/sdhci-of-arasan.c N: zynq N: xilinx diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 275aaa7f3..014281fa2 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1322,6 +1322,20 @@ config I2C_XILINX This driver can also be built as a module. If so, the module will be called xilinx_i2c. +config I2C_XILINX_KUNIT_TEST + bool "KUnit tests for Xilinx I2C register accesses" if !KUNIT_ALL_TESTS + depends on I2C_XILINX && KUNIT=y + default KUNIT_ALL_TESTS + help + Test the Xilinx I2C driver's register accessors with both byte orders + and with native-width or forced 32-bit accesses. KUnit is a kernel + unit testing framework. These tests use memory-backed registers and + do not require an I2C controller. + + The tests are compiled into the driver to exercise its private + accessors, and follow the driver's built-in or module configuration. + If unsure, say N. + config I2C_XLP9XX tristate "Cavium ThunderX2 I2C support" depends on ARCH_THUNDER2 || COMPILE_TEST diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index d13cfb012..f2a77ca8d 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -1650,3 +1650,7 @@ MODULE_ALIAS("platform:" DRIVER_NAME); MODULE_AUTHOR("info@mocean-labs.com"); MODULE_DESCRIPTION("Xilinx I2C bus driver"); MODULE_LICENSE("GPL v2"); + +#if IS_ENABLED(CONFIG_I2C_XILINX_KUNIT_TEST) +#include "tests/i2c_xiic_kunit.c" +#endif diff --git a/drivers/i2c/busses/tests/i2c_xiic_kunit.c b/drivers/i2c/busses/tests/i2c_xiic_kunit.c new file mode 100644 index 000000000..f8df88ca6 --- /dev/null +++ b/drivers/i2c/busses/tests/i2c_xiic_kunit.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Included by i2c-xiic.c to exercise the driver's private accessors. */ +#include + +struct xiic_access_param { + const char *name; + enum xiic_endian endianness; + bool force_32bit_access; +}; + +static const struct xiic_access_param xiic_access_params[] = { + { "native_little_endian", LITTLE, false }, + { "native_big_endian", BIG, false }, + { "word_little_endian", LITTLE, true }, + { "word_big_endian", BIG, true }, +}; + +KUNIT_ARRAY_PARAM_DESC(xiic_access, xiic_access_params, name); + +static void xiic_register_access(struct kunit *test) +{ + static const int offsets[] = { + XIIC_DGIER_OFFSET, XIIC_IISR_OFFSET, XIIC_IIER_OFFSET, + XIIC_RESETR_OFFSET, XIIC_CR_REG_OFFSET, XIIC_SR_REG_OFFSET, + XIIC_DTR_REG_OFFSET, XIIC_DRR_REG_OFFSET, XIIC_ADR_REG_OFFSET, + XIIC_TFO_REG_OFFSET, XIIC_RFO_REG_OFFSET, XIIC_TBA_REG_OFFSET, + XIIC_RFD_REG_OFFSET, XIIC_GPO_REG_OFFSET, XIIC_TSUSTA_REG_OFFSET, + XIIC_TSUSTO_REG_OFFSET, XIIC_THDSTA_REG_OFFSET, + XIIC_TSUDAT_REG_OFFSET, XIIC_TBUF_REG_OFFSET, + XIIC_THIGH_REG_OFFSET, XIIC_TLOW_REG_OFFSET, + XIIC_THDDAT_REG_OFFSET, + }; + const struct xiic_access_param *param = test->param_value; + struct xiic_i2c *i2c; + u32 expected; + u8 *mem; + size_t i; + int reg; + + i2c = kunit_kzalloc(test, sizeof(*i2c), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, i2c); + mem = kunit_kmalloc(test, 0x200, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, mem); + /* Aligned RAM stands in for MMIO. No hardware is accessed. */ + i2c->base = (void __force __iomem *)(mem + sizeof(u32)); + i2c->endianness = param->endianness; + i2c->force_32bit_access = param->force_32bit_access; + + for (i = 0; i < ARRAY_SIZE(offsets); i++) { + reg = offsets[i]; + memset(mem, 0xa5, 0x200); + + xiic_setreg8(i2c, reg, 0xc0); + expected = param->force_32bit_access ? 0xc0 : 0xa5a5a5c0; + KUNIT_EXPECT_EQ(test, (u32)xiic_getreg32(i2c, reg), expected); + KUNIT_EXPECT_EQ(test, xiic_getreg8(i2c, reg), (u8)0xc0); + + xiic_setreg16(i2c, reg, 0x03ff); + expected = param->force_32bit_access ? 0x03ff : 0xa5a503ff; + KUNIT_EXPECT_EQ(test, (u32)xiic_getreg32(i2c, reg), expected); + KUNIT_EXPECT_EQ(test, xiic_getreg8(i2c, reg), (u8)0xff); + + xiic_setreg32(i2c, reg, 0x12345678); + KUNIT_EXPECT_EQ(test, (u32)xiic_getreg32(i2c, reg), 0x12345678U); + KUNIT_EXPECT_EQ(test, xiic_getreg8(i2c, reg), (u8)0x78); + KUNIT_EXPECT_EQ(test, mem[reg + sizeof(u32)], + (u8)(param->endianness == BIG ? 0x12 : 0x78)); + KUNIT_EXPECT_EQ(test, mem[reg + sizeof(u32) + 3], + (u8)(param->endianness == BIG ? 0x78 : 0x12)); + xiic_setreg32(i2c, reg, 0x89abcdefU); + KUNIT_EXPECT_EQ(test, (u32)xiic_getreg32(i2c, reg), 0x89abcdefU); + KUNIT_EXPECT_EQ(test, xiic_getreg8(i2c, reg), (u8)0xef); + KUNIT_EXPECT_EQ(test, mem[reg + sizeof(u32) - 1], (u8)0xa5); + KUNIT_EXPECT_EQ(test, mem[reg + 2 * sizeof(u32)], (u8)0xa5); + } +} + +static struct kunit_case xiic_access_test_cases[] = { + KUNIT_CASE_PARAM(xiic_register_access, xiic_access_gen_params), + {} +}; + +static struct kunit_suite xiic_access_test_suite = { + .name = "i2c_xiic", + .test_cases = xiic_access_test_cases, +}; + +kunit_test_suite(xiic_access_test_suite);