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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4983585923bsm10160123f8f.11.2026.11.11.01.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2026 01:29:36 -0800 (PST) Date: Wed, 11 Nov 2026 09:29:35 +0000 From: David Laight To: "Rui Qi" Cc: "Catalin Marinas" , , , , , , , , Subject: Re: [PATCH 2/3] arm64: patching: Fix instruction byte order in aarch64_insn_set() Message-ID: <20261111092935.4d6060ee@pumpkin> In-Reply-To: <3b540bc9-69b3-42a8-8431-75dd6079bf4f@bytedance.com> References: <20261010084721.2197683-1-qirui.001@bytedance.com> <20261010085055.2200241-1-qirui.001@bytedance.com> <3b540bc9-69b3-42a8-8431-75dd6079bf4f@bytedance.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261111_012941_189089_0C1A1561 X-CRM114-Status: GOOD ( 22.66 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-4.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, 11 Nov 2026 14:52:44 +0800 "Rui Qi" wrote: > On 10/16/26 12:57 AM, Catalin Marinas wrote: > > On Sat, Oct 10, 2026 at 04:50:54PM +0800, Rui Qi wrote: > >> aarch64_insn_set() passes the host-endian u32 instruction straight to > >> text_poke_memset(), which memset32()'s it into memory in host byte order. > >> AArch64 instructions must be little-endian in memory, so on a big-endian > >> kernel the written bytes are reversed and the CPU takes an UNDEFINED > >> instruction exception when fetching them. The sibling aarch64_insn_write() > >> already converts with cpu_to_le32(); aarch64_insn_set() does not. > >> > >> This is reachable in-tree: bpf_arch_text_invalidate() fills freed JIT > >> regions with AARCH64_BREAK_FAULT through aarch64_insn_set(), and arm64 > >> selects HAVE_EBPF_JIT without a big-endian guard, so the path is taken on > >> BE kernels with BPF JIT. The direct-fill loop in the same file already > >> cpu_to_le32()'s the constant, confirming the expected byte order. > >> > >> Convert the instruction to little-endian before the memset, mirroring > >> aarch64_insn_write(). On LE the conversion is a no-op, so behaviour is > >> unchanged. > > > > We are just about to remove big-endian support (in 7.4). > > > > Understood. In -next arm64 no longer has a config CPU_BIG_ENDIAN and > nothing selects it, so 1/3 and 2/3 are fixing a configuration that no > longer exists. I'll drop both. Should it still be fixed in the LTS kernels? (or disable BPF JIT for arm BE) David > > 3/3 ("arm64: module: Use text-poke for late PLT/veneer emission") is > independent of the byte-order work: it routes > module_emit_plt_entry() / module_emit_veneer_for_adrp() through > aarch64_insn_copy() so a late livepatch relocation that falls back to > PLT emission does not write into the ROX .plt and Data Abort. That > path is reachable on LE today (klp_write_section_relocs() on a > MODULE_STATE_LIVE patch module), so it is not BE-specific; it carries > Fixes: 91b89a634487 and Cc: stable. > > I'll resend 3/3 as a standalone patch in a new thread. Happy to route > it a particular way if you'd prefer. >